From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16733 invoked by alias); 26 Jan 2013 00:32:16 -0000 Received: (qmail 16713 invoked by uid 22791); 26 Jan 2013 00:32:14 -0000 X-SWARE-Spam-Status: No, hits=-4.5 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,TW_EQ X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 26 Jan 2013 00:31:42 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1TytgL-0007fK-J0 from Maciej_Rozycki@mentor.com ; Fri, 25 Jan 2013 16:31:41 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 25 Jan 2013 16:31:40 -0800 Received: from [172.30.4.23] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Sat, 26 Jan 2013 00:31:39 +0000 Date: Sat, 26 Jan 2013 00:32:00 -0000 From: "Maciej W. Rozycki" To: Steve Ellcey CC: "libc-alpha@sourceware.org" , "libc-ports@sourceware.org" , Chung-Lin Tang Subject: RE: [PATCH 2/2] MIPS16: MIPS16 support proper In-Reply-To: <1359151771.11963.200.camel@ubuntu-sellcey> Message-ID: References: <1359151771.11963.200.camel@ubuntu-sellcey> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org X-SW-Source: 2013-01/txt/msg00062.txt.bz2 On Fri, 25 Jan 2013, Steve Ellcey wrote: > > Please also note that as I mentioned along the patch submission mixing > > execution modes in static constructors or destructors installed as single > > lumps of code (that is with the use of the DT_INIT or DT_FINI dynamic > > tags) cannot be supported. Can you run `objdump -j .init -j .fini -d' on > > your binary and make sure the disassembly looks right? > > Mine looks a bit different, this is the .init and .fini from a > dynamically linked big endian hello world program, I am not sure where > the addiu instructions are coming from. You have some standard MIPS code there, this is not ever going to work unless we switch to DT_INIT_ARRAY and DT_FINI_ARRAY constructors/destructors. Until then you need to rebuild the relevant sources as MIPS16 code. > x: file format elf32-tradbigmips > > > Disassembly of section .init: > > 004004d0 <_init>: > 4004d0: f000 6a02 li v0,2 > 4004d4: f2f0 0b0c la v1,3f87c0 <_DYNAMIC-0x7a08> > 4004d8: f400 3240 sll v0,16 > 4004dc: e269 addu v0,v1 > 4004de: 64c4 save 32,ra > 4004e0: 659a move gp,v0 > 4004e2: d204 sw v0,16(sp) > 4004e4: f030 9a64 lw v1,-32732(v0) > 4004e8: 2304 beqz v1,4004f2 <_init+0x22> > 4004ea: f030 9a44 lw v0,-32732(v0) > 4004ee: ea40 jalr v0 > 4004f0: 653a move t9,v0 > 4004f2: 6500 nop > 4004f4: 0411 addiu a0,sp,68 > 4004f6: 0001 addiu s0,sp,4 > 4004f8: 0000 addiu s0,sp,0 > 4004fa: 0000 addiu s0,sp,0 > 4004fc: 7410 cmpi a0,16 > 4004fe: 0196 addiu s1,sp,600 > 400500: 0000 addiu s0,sp,0 > 400502: 0000 addiu s0,sp,0 > 400504: 0411 addiu a0,sp,68 > 400506: 0001 addiu s0,sp,4 > 400508: 0000 addiu s0,sp,0 > 40050a: 0000 addiu s0,sp,0 > 40050c: 7410 cmpi a0,16 > 40050e: 01c0 addiu s1,sp,768 > 400510: 0000 addiu s0,sp,0 > 400512: 0000 addiu s0,sp,0 > 400514: 6444 restore 32,ra > 400516: e8a0 jrc ra > > Disassembly of section .fini: > > 00400730 <_fini>: > 400730: f000 6a02 li v0,2 > 400734: f090 0b0c la v1,3f87c0 <_DYNAMIC-0x7a08> > 400738: f400 3240 sll v0,16 > 40073c: e269 addu v0,v1 > 40073e: 64c4 save 32,ra > 400740: 659a move gp,v0 > 400742: d204 sw v0,16(sp) > 400744: 0411 addiu a0,sp,68 > 400746: 0001 addiu s0,sp,4 > 400748: 0000 addiu s0,sp,0 > 40074a: 0000 addiu s0,sp,0 > 40074c: 7410 cmpi a0,16 > 40074e: 0182 addiu s1,sp,520 > 400750: 0000 addiu s0,sp,0 > 400752: 0000 addiu s0,sp,0 > 400754: 6444 restore 32,ra > 400756: e8a0 jrc ra The odd instructions disassemble as follows when interpreted as standard MIPS code: 0: 04110001 bal 8 4: 00000000 nop 8: 74100196 jalx 400658 c: 00000000 nop 10: 04110001 bal 18 14: 00000000 nop 18: 741001c0 jalx 400700 1c: 00000000 nop and: 0: 04110001 bal 8 4: 00000000 nop 8: 74100182 jalx 400608 c: 00000000 nop Make sure that you've got your GCC pieces of the MIPS16 multilib right (crtbegin.o and crtend.o files). Maciej