From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2897 invoked by alias); 21 Aug 2013 21:42:10 -0000 Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org Received: (qmail 2882 invoked by uid 89); 21 Aug 2013 21:42:09 -0000 X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.2 Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 21 Aug 2013 21:42:08 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1VCGAJ-0001PF-4i from Maciej_Rozycki@mentor.com for libc-ports@sourceware.org; Wed, 21 Aug 2013 14:42:07 -0700 Received: from SVR-IES-FEM-02.mgc.mentorg.com ([137.202.0.106]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 21 Aug 2013 14:42:07 -0700 Received: from [172.30.64.90] (137.202.0.76) by SVR-IES-FEM-02.mgc.mentorg.com (137.202.0.106) with Microsoft SMTP Server id 14.2.247.3; Wed, 21 Aug 2013 22:42:04 +0100 Date: Wed, 21 Aug 2013 21:42:00 -0000 From: "Maciej W. Rozycki" To: Subject: [PATCH] MIPS: Correct the handling of reserved FCSR bits Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-SW-Source: 2013-08/txt/msg00025.txt.bz2 Hi, Reserved bits in the Floating-Point Control and Status Register (FCSR) should not be implicitly cleared by fedisableexcept or feenableexcept, there is no reason to. Among these are the 8 condition codes and one of the two bits reserved for architecture implementers (bits #22 & #21). As to the latter, there is no reason to treat any of them as reserved either, they should be user controllable and settable via __fpu_control override as the user sees fit. For example in processors implemented by MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to change the treatment of denormalised operands and tiny results: bit #22 is Flush Override (FO) and bit #21 is Flush to Nearest (FN). They cause non-IEEE-compliant behaviour, but some programs may have a use for such modes of operation; the library should not obstruct such use just as it does not for the architectural Flush to Zero (FS) bit (bit #24). Therefore the change adjusts the reserved mask accordingly and also documents the distinction between bits 22:21 and 20:18. No regressions in mips-linux-gnu testing, o32, n64 and n32 ABIs. OK to apply? 2013-08-21 Maciej W. Rozycki * sysdeps/mips/fpu_control.h: Document bits reserved for architecture implementers. (_FPU_RESERVED): Clear bit #21. * sysdeps/mips/fpu/fedisblxcpt.c (fedisableexcept): Don't clear reserved bits. * sysdeps/mips/fpu/feenablxcpt.c (feenableexcept): Likewise. Maciej glibc-ports-mips-fpucw-reserved-fix.diff Index: glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu_control.h =================================================================== --- glibc-fsf-trunk-quilt.orig/ports/sysdeps/mips/fpu_control.h 2012-12-12 04:15:35.577266033 +0000 +++ glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu_control.h 2012-12-12 04:21:05.767771840 +0000 @@ -28,7 +28,8 @@ * causing unimplemented operation exception. This bit is only * available for MIPS III and newer. * 23 -> Condition bit - * 22-18 -> reserved (read as 0, write with 0) + * 22-21 -> reserved for architecture implementers + * 20-18 -> reserved (read as 0, write with 0) * 17 -> cause bit for unimplemented operation * 16 -> cause bit for invalid exception * 15 -> cause bit for division by zero exception @@ -84,7 +85,7 @@ extern fpu_control_t __fpu_control; #define _FPU_RC_UP 0x2 #define _FPU_RC_DOWN 0x3 -#define _FPU_RESERVED 0xfebc0000 /* Reserved bits in cw */ +#define _FPU_RESERVED 0xfe9c0000 /* Reserved bits in cw */ /* The fdlibm code requires strict IEEE double precision arithmetic, Index: glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu/fedisblxcpt.c =================================================================== --- glibc-fsf-trunk-quilt.orig/ports/sysdeps/mips/fpu/fedisblxcpt.c 2012-12-12 04:14:02.946552647 +0000 +++ glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu/fedisblxcpt.c 2012-12-12 04:21:05.767771840 +0000 @@ -34,7 +34,6 @@ fedisableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_exc &= ~(excepts << ENABLE_SHIFT); - new_exc &= ~_FPU_RESERVED; _FPU_SETCW (new_exc); return old_exc; Index: glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu/feenablxcpt.c =================================================================== --- glibc-fsf-trunk-quilt.orig/ports/sysdeps/mips/fpu/feenablxcpt.c 2012-12-12 04:14:02.946552647 +0000 +++ glibc-fsf-trunk-quilt/ports/sysdeps/mips/fpu/feenablxcpt.c 2012-12-12 04:21:05.767771840 +0000 @@ -34,7 +34,6 @@ feenableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_exc |= excepts << ENABLE_SHIFT; - new_exc &= ~_FPU_RESERVED; _FPU_SETCW (new_exc); return old_exc;