From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id CD46F3858C3A for ; Mon, 10 Jan 2022 21:50:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD46F3858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=none smtp.mailfrom=aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=P9qun1WQLN8tWkfFNj5vzHe5+8bYm9Nqn2OrLpt1CEU=; b=kiTjnDozcBBSTeLvvrjWPcG73S NOMU6aB7WibKtgGUZmdwy7QxHFgWJ9JpdGQRO4WRkZESr0bXz6qO1ppcYSKYHV4M4vqsQovup+MWG 8n36w2/VFRpqTzdjG9hiTY10C351Ngv4DPuXXxsxIx2yINmGk3Iz9ERIgn5B2xVKRc2KqJA6w1whD oxbanKAYUMx8+E4/6/iwEaBfc3ggQ3ccyCHSnwHB/ltH8giAFLj8/pHUe7xyNK402pvtXtLKYv8aM TR/wkH90+UboQd/mI3dbtsD4KaAuKi3Rgwj1TlHGMqG5BO5AaN3R/K+XiytvmwO5aEKwNrLHWMSHt YXjogzCQ==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n72Yo-005ubX-Nj; Mon, 10 Jan 2022 22:50:38 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.95) (envelope-from ) id 1n72Yo-0052rU-8R; Mon, 10 Jan 2022 22:50:38 +0100 From: Aurelien Jarno To: libc-stable@sourceware.org Cc: "Paul A. Clarke" , Tulio Magno Quites Machado Filho Subject: [COMMITTED 2.33] powerpc: Fix unrecognized instruction errors with recent GCC Date: Mon, 10 Jan 2022 22:50:30 +0100 Message-Id: <20220110215030.1202608-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-stable@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-stable mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Jan 2022 21:50:41 -0000 From: "Paul A. Clarke" Recent binutils commit b25f942e18d6ecd7ec3e2d2e9930eb4f996c258a changes the behavior of `.machine` directives to override, rather than augment, the base CPU. This can result in _reduced_ functionality when, for example, compiling for default machine "power8", but explicitly asking for ".machine power5", which loses Altivec instructions. In tst-ucontext-ppc64-vscr.c, while the instructions provoking the new error messages are bracketed by ".machine power5", which is ostensibly Power ISA 2.03 (POWER5), the POWER5 processor did not support the VSX subset, so these instructions are not recognized as "power5". Error: unrecognized opcode: `vspltisb' Error: unrecognized opcode: `vpkuwus' Error: unrecognized opcode: `mfvscr' Error: unrecognized opcode: `stvx' Manually adding the VSX subset via ".machine altivec" is sufficient. Reviewed-by: Tulio Magno Quites Machado Filho (cherry picked from commit 064b475a2e5662b6b3973fabf505eade86e61510) --- sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c index 28c87fcef7..d3fc4ab589 100644 --- a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c +++ b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c @@ -50,6 +50,7 @@ do_test (void) /* Set SAT bit in VSCR register. */ asm volatile (".machine push;\n" ".machine \"power5\";\n" + ".machine altivec;\n" "vspltisb %0,0;\n" "vspltisb %1,-1;\n" "vpkuwus %0,%0,%1;\n" -- 2.34.1