From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id AA02A3858D3C for ; Tue, 18 Jan 2022 06:45:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AA02A3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=none smtp.mailfrom=aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=ukAT0go83jTpKrGlBzxweOD97wcZ42dQ3IL+Y2NdKIc=; b=HawMmKTm545LHf5pyAMzod2x4n sI9R2zP1LWhJc5oTSKPUd1nRMmXgKVVGJlw/DnPbo+zzJ5zUT8yD7vbLL+NtdctNg8quk2bLlLe1/ VxS3hXgY7LtJsd5tEJEtUBxFd11upc7eBYAv5wkXLw8H2GV9LdNXRh8SNqV/DC/si15PlkYp1JA2k +yhpIsFx55SNvzNz80sN1iZbk0JXx7iUFrheMPpogagkp6+Y9dXrJ2yoIHjc/Wem8SgmEQ9QPGNxw x3/OZpZXPXzV/8xzhb+LSAR1GGpbcAQ9QQkhZOgbBAYYJlfli/4F1seQpJGE4UhqrAmSNzN03FTJN XlGPJRWA==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n9iFS-00AmGl-Bz; Tue, 18 Jan 2022 07:45:42 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.95) (envelope-from ) id 1n9iFP-004rmc-TP; Tue, 18 Jan 2022 07:45:39 +0100 From: Aurelien Jarno To: libc-stable@sourceware.org Cc: Aurelien Jarno , "H . J . Lu" Subject: [COMMITTED 2.33] x86: use default cache size if it cannot be determined [BZ #28784] Date: Tue, 18 Jan 2022 07:45:38 +0100 Message-Id: <20220118064538.1160022-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-stable@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-stable mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Jan 2022 06:45:45 -0000 In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can not be retrieved and the corresponding values are set to 0. Commit 2d651eb9265d ("x86: Move x86 processor cache info to cpu_features") changed the behaviour in such case by defining the __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead of using the default values. This cause an issue with the i686 SSE2 optimized bzero/routine which assumes that the cache size is at least 128 bytes, and otherwise tries to zero/set the whole address space minus 128 bytes. Fix that by restoring the original code to only update __x86_shared_cache_size and __x86_data_cache_size variables if the corresponding cache sizes are not zero. Fixes bug 28784 Fixes commit 2d651eb9265d Reviewed-by: H.J. Lu (cherry picked from commit c242fcce06e3102ca663b2f992611d0bda4f2668) --- NEWS | 1 + sysdeps/x86/cacheinfo.h | 14 ++++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/NEWS b/NEWS index 6091d5bd82..6e4221ca86 100644 --- a/NEWS +++ b/NEWS @@ -271,6 +271,7 @@ The following bugs are resolved with this release: [27237] malloc: deadlock in malloc/tst-malloc-stats-cancellation [27256] locale: Assertion failure in ISO-2022-JP-3 gconv module related to combining characters (CVE-2021-3326) + [28784] x86: crash in 32bit memset-sse2.s when the cache size can not be determined Version 2.32 diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h index 68c253542f..0f850bdf12 100644 --- a/sysdeps/x86/cacheinfo.h +++ b/sysdeps/x86/cacheinfo.h @@ -63,16 +63,22 @@ init_cacheinfo (void) __x86_raw_data_cache_size = data; /* Round data cache size to multiple of 256 bytes. */ data = data & ~255L; - __x86_data_cache_size_half = data / 2; - __x86_data_cache_size = data; + if (data > 0) + { + __x86_data_cache_size_half = data / 2; + __x86_data_cache_size = data; + } long int shared = cpu_features->shared_cache_size; __x86_raw_shared_cache_size_half = shared / 2; __x86_raw_shared_cache_size = shared; /* Round shared cache size to multiple of 256 bytes. */ shared = shared & ~255L; - __x86_shared_cache_size_half = shared / 2; - __x86_shared_cache_size = shared; + if (shared > 0) + { + __x86_shared_cache_size_half = shared / 2; + __x86_shared_cache_size = shared; + } __x86_shared_non_temporal_threshold = cpu_features->non_temporal_threshold; -- 2.34.1