From: Arjun Shankar <arjun@redhat.com>
To: libc-stable@sourceware.org
Cc: Arjun Shankar <arjun@redhat.com>,
Adhemerval Zanella <adhemerval.zanella@linaro.org>,
"H . J . Lu" <hjl.tools@gmail.com>
Subject: [COMMITTED 2.39 3/3] x86: Expand the comment on when REP STOSB is used on memset
Date: Thu, 4 Apr 2024 12:39:58 +0200 [thread overview]
Message-ID: <20240404103958.311687-3-arjun@redhat.com> (raw)
In-Reply-To: <20240404103958.311687-1-arjun@redhat.com>
From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
(cherry picked from commit 491e55beab7457ed310a4a47496f4a333c5d1032)
---
sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
index 9984c3ca0f..97839a2248 100644
--- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
+++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
@@ -21,7 +21,9 @@
2. If size is less than VEC, use integer register stores.
3. If size is from VEC_SIZE to 2 * VEC_SIZE, use 2 VEC stores.
4. If size is from 2 * VEC_SIZE to 4 * VEC_SIZE, use 4 VEC stores.
- 5. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
+ 5. On machines ERMS feature, if size is greater or equal than
+ __x86_rep_stosb_threshold then REP STOSB will be used.
+ 6. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with
4 VEC stores and store 4 * VEC at a time until done. */
#include <sysdep.h>
--
2.43.0
prev parent reply other threads:[~2024-04-04 10:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 10:39 [COMMITTED 2.39 1/3] x86: Fix Zen3/Zen4 ERMS selection (BZ 30994) Arjun Shankar
2024-04-04 10:39 ` [COMMITTED 2.39 2/3] x86: Do not prefer ERMS for memset on Zen3+ Arjun Shankar
2024-04-04 10:39 ` Arjun Shankar [this message]
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