From: "H.J. Lu" <hjl.tools@gmail.com>
To: Noah Goldstein <goldstein.w.n@gmail.com>
Cc: GNU C Library <libc-alpha@sourceware.org>,
"Carlos O'Donell" <carlos@redhat.com>,
Libc-stable Mailing List <libc-stable@sourceware.org>
Subject: Re: [PATCH v2] x86: Black list more Intel CPUs for TSX [BZ #27398]
Date: Tue, 1 Feb 2022 05:42:35 -0800 [thread overview]
Message-ID: <CAMe9rOrNncLmEKjf+FV99TXxpBLDcLPGidxPU5xjfFK7OcjuEw@mail.gmail.com> (raw)
In-Reply-To: <CAFUsyfL4Tw=KZUSdmGLDBsDW7aOaSFC2RmJd58SxxpXxh2Ef8Q@mail.gmail.com>
On Tue, Jan 18, 2022 at 1:51 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Tue, Jan 18, 2022 at 3:29 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in:
> >
> > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
> >
> > This fixes BZ #27398.
> > ---
> > sysdeps/x86/cpu-features.c | 34 +++++++++++++++++++++++++++++++---
> > 1 file changed, 31 insertions(+), 3 deletions(-)
> >
> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > index 772ccf8e91..514226b378 100644
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -507,11 +507,39 @@ init_cpu_features (struct cpu_features *cpu_features)
> > break;
> > }
> >
> > - /* Disable TSX on some Haswell processors to avoid TSX on kernels that
> > - weren't updated with the latest microcode package (which disables
> > - broken feature by default). */
> > + /* Disable TSX on some processors to avoid TSX on kernels that
> > + weren't updated with the latest microcode package (which
> > + disables broken feature by default). */
> > switch (model)
> > {
> > + case 0x55:
> > + if (stepping <= 5)
> > + goto disable_tsx;
> > + break;
> > + case 0x8e:
> > + /* NB: Although the errata documents that for model == 0x8e,
> > + only 0xb stepping or lower are impacted, the intention of
> > + the errata was to disable TSX on all client processors on
> > + all steppings. Include 0xc stepping which is an Intel
> > + Core i7-8665U, a client mobile processor. */
> > + case 0x9e:
> > + if (stepping > 0xc)
> > + break;
> > + /* Fall through. */
> > + case 0x4e:
> > + case 0x5e:
> > + {
> > + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
> > + processors listed in:
> > +
> > +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
> > + */
> > +disable_tsx:
> > + CPU_FEATURE_UNSET (cpu_features, HLE);
> > + CPU_FEATURE_UNSET (cpu_features, RTM);
> > + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
> > + }
> > + break;
> > case 0x3f:
> > /* Xeon E7 v3 with stepping >= 4 has working TSX. */
> > if (stepping >= 4)
> > --
> > 2.34.1
> >
>
> LGTM.
I am backporting this to release branches.
--
H.J.
parent reply other threads:[~2022-02-01 13:43 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <CAFUsyfL4Tw=KZUSdmGLDBsDW7aOaSFC2RmJd58SxxpXxh2Ef8Q@mail.gmail.com>]
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