From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by sourceware.org (Postfix) with ESMTPS id 010853858C2D; Tue, 1 Feb 2022 13:43:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 010853858C2D Received: by mail-pf1-x42e.google.com with SMTP id a19so9950493pfx.4; Tue, 01 Feb 2022 05:43:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lNRbrMgFlj7gX0kKVxMZ4frPUCitD2H/DcjF1JOHUNA=; b=tcBXnOwr7QDIO8JXB3kWndJ2n95UG4g5L+rL4w7Ms4ol6bnaY7U61zHvStf2jSWH9D tgH1DGqqS8fSzLBnZy0k7LgB2bVEQV7RmzyOOo8HuUj3Jii+Nt54Yz9gP8OS/dBxI3Ze dE2i+9+6kK2YX73/32y4IJ8J892Gx8w03jvzMPoNCv+JSqz5kGqXNsLlTCzWTjBx9RgO uKKT/9cu9z/Hxzhb71rbTiyAQO1r/z6f3bDhGr7UbWPjXGsANy5KuZxTwhrk0n9qkou/ 9SaU1Ma4UNWEfz2jcE+/d2Lro51nx4QPthlvrEvqo0bWVfirGieeilxJCkKQqFHdUCOu ePKA== X-Gm-Message-State: AOAM531O0n3dTq6yDVomP94Hthw0z8Dl0qlxQKhSFGlai4uKiaJLOrIF J1cjd2yRAibkzagWhuiwtFZo1s/H8GxQnJYGzNYgpnQdAiI= X-Google-Smtp-Source: ABdhPJxvg823169HU+BlyBA7uR/B8/s/D9Bg1U/RHS8xVIVt70CIAEglKV/4pv8dJHrc6kls2g6N+8cLA2wM++PWVkA= X-Received: by 2002:aa7:888b:: with SMTP id z11mr19424928pfe.76.1643722991095; Tue, 01 Feb 2022 05:43:11 -0800 (PST) MIME-Version: 1.0 References: <20220118212940.2051376-1-hjl.tools@gmail.com> In-Reply-To: From: "H.J. Lu" Date: Tue, 1 Feb 2022 05:42:35 -0800 Message-ID: Subject: Re: [PATCH v2] x86: Black list more Intel CPUs for TSX [BZ #27398] To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" , Libc-stable Mailing List Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3027.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-stable@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-stable mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 13:43:13 -0000 On Tue, Jan 18, 2022 at 1:51 PM Noah Goldstein wrote: > > On Tue, Jan 18, 2022 at 3:29 PM H.J. Lu wrote: > > > > Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in: > > > > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > > > > This fixes BZ #27398. > > --- > > sysdeps/x86/cpu-features.c | 34 +++++++++++++++++++++++++++++++--- > > 1 file changed, 31 insertions(+), 3 deletions(-) > > > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > index 772ccf8e91..514226b378 100644 > > --- a/sysdeps/x86/cpu-features.c > > +++ b/sysdeps/x86/cpu-features.c > > @@ -507,11 +507,39 @@ init_cpu_features (struct cpu_features *cpu_features) > > break; > > } > > > > - /* Disable TSX on some Haswell processors to avoid TSX on kernels that > > - weren't updated with the latest microcode package (which disables > > - broken feature by default). */ > > + /* Disable TSX on some processors to avoid TSX on kernels that > > + weren't updated with the latest microcode package (which > > + disables broken feature by default). */ > > switch (model) > > { > > + case 0x55: > > + if (stepping <= 5) > > + goto disable_tsx; > > + break; > > + case 0x8e: > > + /* NB: Although the errata documents that for model == 0x8e, > > + only 0xb stepping or lower are impacted, the intention of > > + the errata was to disable TSX on all client processors on > > + all steppings. Include 0xc stepping which is an Intel > > + Core i7-8665U, a client mobile processor. */ > > + case 0x9e: > > + if (stepping > 0xc) > > + break; > > + /* Fall through. */ > > + case 0x4e: > > + case 0x5e: > > + { > > + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for > > + processors listed in: > > + > > +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > > + */ > > +disable_tsx: > > + CPU_FEATURE_UNSET (cpu_features, HLE); > > + CPU_FEATURE_UNSET (cpu_features, RTM); > > + CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT); > > + } > > + break; > > case 0x3f: > > /* Xeon E7 v3 with stepping >= 4 has working TSX. */ > > if (stepping >= 4) > > -- > > 2.34.1 > > > > LGTM. I am backporting this to release branches. -- H.J.