From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
To: "libc-stable@sourceware.org" <libc-stable@sourceware.org>
Cc: nd <nd@arm.com>
Subject: [2.27 COMMITTED][AArch64] Backport ifunc support for Ares
Date: Tue, 01 Jan 2019 00:00:00 -0000 [thread overview]
Message-ID: <VI1PR0801MB21278AD00A2236CB11E519D683BA0@VI1PR0801MB2127.eurprd08.prod.outlook.com> (raw)
commit 5f0d2e049114a1cb5bac11a2a22a4833692ab0cd
Author: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Date: Wed Dec 19 18:28:24 2018 +0000
[AArch64] Add ifunc support for Ares
Add Ares to the midr_el0 list and support ifunc dispatch. Since Ares
supports 2 128-bit loads/stores, use Neon registers for memcpy by
selecting __memcpy_falkor by default (we should rename this to
__memcpy_simd or similar).
* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
__memcpy_falkor for ares.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
Add new define.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
Add ares cpu.
(cherry picked from commit 02f440c1ef5d5d79552a524065aa3e2fabe469b9)
diff --git a/ChangeLog b/ChangeLog
index dd2106c..3265e61 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+2019-09-06 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * manual/tunables.texi (glibc.cpu.name): Add ares tunable.
+ * sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
+ __memcpy_falkor for ares.
+ * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
+ Add new define.
+ * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
+ Add ares cpu.
+
2019-09-06 Siddhesh Poyarekar <siddhesh@sourceware.org>
* sysdeps/aarch64/multiarch/memcpy_falkor.S (__memcpy_falkor):
diff --git a/manual/tunables.texi b/manual/tunables.texi
index a310e38..8506833 100644
--- a/manual/tunables.texi
+++ b/manual/tunables.texi
@@ -333,7 +333,7 @@ This tunable is specific to powerpc, powerpc64 and powerpc64le.
The @code{glibc.tune.cpu=xxx} tunable allows the user to tell @theglibc{} to
assume that the CPU is @code{xxx} where xxx may have one of these values:
@code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99},
-@code{thunderx2t99p1}.
+@code{thunderx2t99p1}, @code{ares}.
This tunable is specific to aarch64.
@end deftp
diff --git a/sysdeps/aarch64/multiarch/memcpy.c b/sysdeps/aarch64/multiarch/memcpy.c
index 3efea2c..abeca6c 100644
--- a/sysdeps/aarch64/multiarch/memcpy.c
+++ b/sysdeps/aarch64/multiarch/memcpy.c
@@ -35,7 +35,7 @@ extern __typeof (__redirect_memcpy) __memcpy_falkor attribute_hidden;
libc_ifunc (__libc_memcpy,
(IS_THUNDERX (midr)
? __memcpy_thunderx
- : (IS_FALKOR (midr)
+ : (IS_FALKOR (midr) || IS_ARES (midr)
? __memcpy_falkor
: __memcpy_generic)));
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 33b87a8..e3fb09e 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -35,6 +35,7 @@ static struct cpu_list cpu_list[] = {
{"thunderxt88", 0x430F0A10},
{"thunderx2t99", 0x431F0AF0},
{"thunderx2t99p1", 0x420F5160},
+ {"ares", 0x411FD0C0},
{"generic", 0x0}
};
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
index c646f9d..9e31575 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
@@ -44,6 +44,9 @@
#define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \
&& MIDR_PARTNUM(midr) == 0xc00)
+#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
+ && MIDR_PARTNUM(midr) == 0xd0c)
+
struct cpu_features
{
uint64_t midr_el1;
reply other threads:[~2019-09-06 18:47 UTC|newest]
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