From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 2457C385F019 for ; Tue, 1 Feb 2022 13:57:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2457C385F019 Received: by mail-pj1-x102c.google.com with SMTP id r59so17172710pjg.4 for ; Tue, 01 Feb 2022 05:57:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:subject:message-id:mime-version :content-disposition; bh=tOaMn18tnHbcvLU+VPeV/x5INvBe5jwuzwenGmoipa0=; b=O4clUNbyJ+v92DDIl3R+2lHYS+9+arHr9WktZXJK2wQv77qdKMRiLFTviVTVA6tMvy oNbPT4Eq5bxtnJbkFOkDYkUXi606I5aJJQ5dHi8Ud+x0eroND3tB+k6a81N63UHh8Qki qSw0rDNdNE361N0LmGN3DPzv0Zyg8qphB590rFBFFgL9hNqyujfXMd07W1NpVKGf4LsP uZ9O6Lq1yFNA0nLK4BtSbnid63HqlHrsqK+bkzQCJGZd7JCv49wcYVTuqUayVEJGfllb 2gsptMCU+G41MM2jp0nbpImkLl1TGpuXCIXSXIKaQoA4L9Ln96k1vqgPE598q4EjuYXo af0Q== X-Gm-Message-State: AOAM531vWa8L48UzBU27q/bkPugNqZ8fJxRNltl7HiTOvuL4KySIQvD7 r+6DUNm1SqUyGKQiFPmmiTqNKgkQO639xw== X-Google-Smtp-Source: ABdhPJwiVDpkOeSW6qAa57Jpfh5/cMypvOaO4XuHuR1UdDlsFsUOds99udTZmARYCVD6dfzVdoZyJQ== X-Received: by 2002:a17:90b:817:: with SMTP id bk23mr2426234pjb.134.1643723829921; Tue, 01 Feb 2022 05:57:09 -0800 (PST) Received: from gnu-tgl-3.localdomain ([172.58.38.240]) by smtp.gmail.com with ESMTPSA id k14sm7793639pff.25.2022.02.01.05.57.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 05:57:09 -0800 (PST) Received: by gnu-tgl-3.localdomain (Postfix, from userid 1000) id F12EAC075E; Tue, 1 Feb 2022 05:57:07 -0800 (PST) Date: Tue, 1 Feb 2022 05:57:07 -0800 From: "H.J. Lu" To: libc-stable@sourceware.org Subject: [2.33 and older] [PATCH] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Spam-Status: No, score=-3030.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-stable@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-stable mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 13:57:13 -0000 I am backporting this to 2.33 and older release branches. H.J. --- From https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (RTM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033. (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec) --- manual/platform.texi | 3 +++ sysdeps/x86/bits/platform/x86.h | 2 +- sysdeps/x86/cpu-features.c | 5 ++++- sysdeps/x86/include/cpu-features.h | 6 +++--- sysdeps/x86/tst-cpu-features-supports.c | 2 +- sysdeps/x86/tst-get-cpu-features.c | 2 ++ 6 files changed, 14 insertions(+), 6 deletions(-) diff --git a/manual/platform.texi b/manual/platform.texi index 6caf68d796..3e988261ba 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -510,6 +510,9 @@ capability. @item @code{RTM} -- RTM instruction extensions. +@item +@code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable. + @item @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug. diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h index 8f423ae721..2cf898ff7c 100644 --- a/sysdeps/x86/bits/platform/x86.h +++ b/sysdeps/x86/bits/platform/x86.h @@ -210,7 +210,7 @@ enum x86_cpu_AVX512_VP2INTERSECT = x86_cpu_index_7_edx + 8, x86_cpu_INDEX_7_EDX_9 = x86_cpu_index_7_edx + 9, x86_cpu_MD_CLEAR = x86_cpu_index_7_edx + 10, - x86_cpu_INDEX_7_EDX_11 = x86_cpu_index_7_edx + 11, + x86_cpu_RTM_ALWAYS_ABORT = x86_cpu_index_7_edx + 11, x86_cpu_INDEX_7_EDX_12 = x86_cpu_index_7_edx + 12, x86_cpu_INDEX_7_EDX_13 = x86_cpu_index_7_edx + 13, x86_cpu_SERIALIZE = x86_cpu_index_7_edx + 14, diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index f8de550e8d..bcc9c89502 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -66,7 +66,6 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, HLE); CPU_FEATURE_SET_USABLE (cpu_features, BMI2); CPU_FEATURE_SET_USABLE (cpu_features, ERMS); - CPU_FEATURE_SET_USABLE (cpu_features, RTM); CPU_FEATURE_SET_USABLE (cpu_features, RDSEED); CPU_FEATURE_SET_USABLE (cpu_features, ADX); CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT); @@ -83,6 +82,7 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, MOVDIRI); CPU_FEATURE_SET_USABLE (cpu_features, MOVDIR64B); CPU_FEATURE_SET_USABLE (cpu_features, FSRM); + CPU_FEATURE_SET_USABLE (cpu_features, RTM_ALWAYS_ABORT); CPU_FEATURE_SET_USABLE (cpu_features, SERIALIZE); CPU_FEATURE_SET_USABLE (cpu_features, TSXLDTRK); CPU_FEATURE_SET_USABLE (cpu_features, IBT); @@ -97,6 +97,9 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, FSRS); CPU_FEATURE_SET_USABLE (cpu_features, FSRCS); + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT)) + CPU_FEATURE_SET_USABLE (cpu_features, RTM); + /* Can we call xgetbv? */ if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE)) { diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 04d8e5734e..bfe4fe231e 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -229,7 +229,7 @@ enum #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) #define bit_cpu_INDEX_7_EDX_9 (1u << 9) #define bit_cpu_MD_CLEAR (1u << 10) -#define bit_cpu_INDEX_7_EDX_11 (1u << 11) +#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11) #define bit_cpu_INDEX_7_EDX_12 (1u << 12) #define bit_cpu_INDEX_7_EDX_13 (1u << 13) #define bit_cpu_SERIALIZE (1u << 14) @@ -454,7 +454,7 @@ enum #define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7 #define index_cpu_MD_CLEAR CPUID_INDEX_7 -#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7 +#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7 #define index_cpu_SERIALIZE CPUID_INDEX_7 @@ -679,7 +679,7 @@ enum #define reg_AVX512_VP2INTERSECT edx #define reg_INDEX_7_EDX_9 edx #define reg_MD_CLEAR edx -#define reg_INDEX_7_EDX_11 edx +#define reg_RTM_ALWAYS_ABORT edx #define reg_INDEX_7_EDX_12 edx #define reg_INDEX_7_EDX_13 edx #define reg_SERIALIZE edx diff --git a/sysdeps/x86/tst-cpu-features-supports.c b/sysdeps/x86/tst-cpu-features-supports.c index cc0d2b2d56..871fe4d265 100644 --- a/sysdeps/x86/tst-cpu-features-supports.c +++ b/sysdeps/x86/tst-cpu-features-supports.c @@ -152,7 +152,7 @@ do_test (int argc, char **argv) fails += CHECK_SUPPORTS (rdpid, RDPID); fails += CHECK_SUPPORTS (rdrnd, RDRAND); fails += CHECK_SUPPORTS (rdseed, RDSEED); - fails += CHECK_SUPPORTS (rtm, RTM); + fails += CHECK_CPU_SUPPORTS (rtm, RTM); fails += CHECK_SUPPORTS (serialize, SERIALIZE); fails += CHECK_SUPPORTS (sha, SHA); fails += CHECK_CPU_SUPPORTS (shstk, SHSTK); diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index b5e7f6e7b0..37d9ec9d8c 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -158,6 +158,7 @@ do_test (void) CHECK_CPU_FEATURE (UINTR); CHECK_CPU_FEATURE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE (MD_CLEAR); + CHECK_CPU_FEATURE (RTM_ALWAYS_ABORT); CHECK_CPU_FEATURE (SERIALIZE); CHECK_CPU_FEATURE (HYBRID); CHECK_CPU_FEATURE (TSXLDTRK); @@ -321,6 +322,7 @@ do_test (void) CHECK_CPU_FEATURE_USABLE (FSRM); CHECK_CPU_FEATURE_USABLE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE_USABLE (MD_CLEAR); + CHECK_CPU_FEATURE_USABLE (RTM_ALWAYS_ABORT); CHECK_CPU_FEATURE_USABLE (SERIALIZE); CHECK_CPU_FEATURE_USABLE (HYBRID); CHECK_CPU_FEATURE_USABLE (TSXLDTRK); -- 2.34.1