From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31457 invoked by alias); 28 Oct 2014 18:54:01 -0000 Mailing-List: contact libffi-discuss-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libffi-discuss-owner@sourceware.org Received: (qmail 31377 invoked by uid 89); 28 Oct 2014 18:54:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qc0-f170.google.com Received: from mail-qc0-f170.google.com (HELO mail-qc0-f170.google.com) (209.85.216.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 28 Oct 2014 18:54:00 +0000 Received: by mail-qc0-f170.google.com with SMTP id l6so1109228qcy.15 for ; Tue, 28 Oct 2014 11:53:57 -0700 (PDT) X-Received: by 10.140.35.85 with SMTP id m79mr7527078qgm.81.1414522435944; Tue, 28 Oct 2014 11:53:55 -0700 (PDT) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id 69sm1717430qgy.19.2014.10.28.11.53.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Oct 2014 11:53:55 -0700 (PDT) From: Richard Henderson To: libffi-discuss@sourceware.org Cc: Richard Henderson Subject: [PATCH 06/16] aarch64: Use correct return registers Date: Tue, 28 Oct 2014 18:54:00 -0000 Message-Id: <1414522393-19169-7-git-send-email-rth@twiddle.net> In-Reply-To: <1414522393-19169-1-git-send-email-rth@twiddle.net> References: <1414522393-19169-1-git-send-email-rth@twiddle.net> X-SW-Source: 2014/txt/msg00139.txt.bz2 From: Richard Henderson There are fewer return registers than argument registers. --- src/aarch64/sysv.S | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/src/aarch64/sysv.S b/src/aarch64/sysv.S index 70870db..fa7ff5b 100644 --- a/src/aarch64/sysv.S +++ b/src/aarch64/sysv.S @@ -160,22 +160,15 @@ CNAME(ffi_call_SYSV): blr x24 - /* Save the core argument passing registers. */ - stp x0, x1, [x21, #16*N_V_ARG_REG + 0] - stp x2, x3, [x21, #16*N_V_ARG_REG + 16] - stp x4, x5, [x21, #16*N_V_ARG_REG + 32] - stp x6, x7, [x21, #16*N_V_ARG_REG + 48] - - /* Note nothing useful ever comes back in x8! */ + /* Save the core return registers. */ + stp x0, x1, [x21, #16*N_V_ARG_REG] /* Figure out if we should touch the vector registers. */ tbz x23, #AARCH64_FLAG_ARG_V_BIT, 1f - /* Save the vector argument passing registers. */ + /* Save the vector return registers. */ stp q0, q1, [x21, #0] stp q2, q3, [x21, #32] - stp q4, q5, [x21, #64] - stp q6, q7, [x21, #96] 1: /* All done, unwind our stack frame. */ ldp x21, x22, [x29, # - ffi_call_SYSV_FS] @@ -299,15 +292,9 @@ CNAME(ffi_closure_SYSV): /* Load the result passing vector registers. */ ldp q0, q1, [x21, #0] ldp q2, q3, [x21, #32] - ldp q4, q5, [x21, #64] - ldp q6, q7, [x21, #96] 1: /* Load the result passing core registers. */ ldp x0, x1, [x21, #16*N_V_ARG_REG + 0] - ldp x2, x3, [x21, #16*N_V_ARG_REG + 16] - ldp x4, x5, [x21, #16*N_V_ARG_REG + 32] - ldp x6, x7, [x21, #16*N_V_ARG_REG + 48] - /* Note nothing useful is returned in x8. */ /* We are done, unwind our frame. */ ldp x21, x22, [x29, #-16] -- 1.9.3