From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2062) id DFE0C3858C74; Tue, 1 Feb 2022 17:04:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DFE0C3858C74 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Thomas Rodgers To: gcc-cvs@gcc.gnu.org, libstdc++-cvs@gcc.gnu.org Subject: [gcc r12-6964] Strengthen memory order for atomic::wait/notify X-Act-Checkin: gcc X-Git-Author: Thomas Rodgers X-Git-Refname: refs/heads/master X-Git-Oldrev: 3ad29854f0b2b1f468ea87e8cbd2a5c5a72ba5fe X-Git-Newrev: 07a971b28c880938bb7e070465ab8ee6ccdad1fb Message-Id: <20220201170432.DFE0C3858C74@sourceware.org> Date: Tue, 1 Feb 2022 17:04:32 +0000 (GMT) X-BeenThere: libstdc++-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libstdc++-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Feb 2022 17:04:33 -0000 https://gcc.gnu.org/g:07a971b28c880938bb7e070465ab8ee6ccdad1fb commit r12-6964-g07a971b28c880938bb7e070465ab8ee6ccdad1fb Author: Thomas Rodgers Date: Mon Jan 31 13:39:44 2022 -0800 Strengthen memory order for atomic::wait/notify This matches the memory order in libc++. libstdc++-v3/ChangeLog: * include/bits/atomic_wait.h: Change memory order from Acquire/Release with relaxed loads to SeqCst+Release for accesses to the waiter's count. Diff: --- libstdc++-v3/include/bits/atomic_wait.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libstdc++-v3/include/bits/atomic_wait.h b/libstdc++-v3/include/bits/atomic_wait.h index 05cf0013d2a..d7de0d7eb9e 100644 --- a/libstdc++-v3/include/bits/atomic_wait.h +++ b/libstdc++-v3/include/bits/atomic_wait.h @@ -209,18 +209,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION void _M_enter_wait() noexcept - { __atomic_fetch_add(&_M_wait, 1, __ATOMIC_ACQ_REL); } + { __atomic_fetch_add(&_M_wait, 1, __ATOMIC_SEQ_CST); } void _M_leave_wait() noexcept - { __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_ACQ_REL); } + { __atomic_fetch_sub(&_M_wait, 1, __ATOMIC_RELEASE); } bool _M_waiting() const noexcept { __platform_wait_t __res; - __atomic_load(&_M_wait, &__res, __ATOMIC_ACQUIRE); - return __res > 0; + __atomic_load(&_M_wait, &__res, __ATOMIC_SEQ_CST); + return __res != 0; } void @@ -258,7 +258,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __platform_wait(__addr, __old); #else __platform_wait_t __val; - __atomic_load(__addr, &__val, __ATOMIC_RELAXED); + __atomic_load(__addr, &__val, __ATOMIC_SEQ_CST); if (__val == __old) { lock_guard __l(_M_mtx); @@ -309,7 +309,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { if (_M_laundered()) { - __atomic_fetch_add(_M_addr, 1, __ATOMIC_ACQ_REL); + __atomic_fetch_add(_M_addr, 1, __ATOMIC_SEQ_CST); __all = true; } _M_w._M_notify(_M_addr, __all, __bare);