[gcc r13-2194] Daily bump.

[gcc r13-2194] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:e8fc33aabcfd8f4a4e384e022e4812caca556e0e

commit r13-2194-ge8fc33aabcfd8f4a4e384e022e4812caca556e0e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Thu Aug 25 00:16:33 2022 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 205 ++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/fortran/ChangeLog   |   6 ++
 gcc/testsuite/ChangeLog |  60 ++++++++++++++
 libcpp/ChangeLog        |   8 ++
 libstdc++-v3/ChangeLog  |  57 ++++++++++++++
 6 files changed, 337 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c07208a2e2f..4a99f8a6bfd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,208 @@
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106632
+	PR target/106588
+	* config/riscv/bitmanip.md (*shNadduw): Use n constraint
+	instead of i.
+	(*slliuw): Likewise.
+	(*bexti): Likewise. Also add a check for operands[2] to be less
+	than the mode bitsize.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/constraints.md (DbS): New constraint.
+	(DnS): New constraint.
+	* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
+	(*bclr<mode>): Likewise.
+	(*binvi<mode>): Likewise.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106586
+	* config/riscv/predicates.md (single_bit_mask_operand):
+	Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi.
+	(not_single_bit_mask_operand): Likewise.
+	* config/riscv/riscv.cc (riscv_build_integer_1): Don't special case
+	1<<31 for 32bits as it is already handled.
+	Call trunc_int_for_mode on the upper part after the subtraction.
+	(riscv_move_integer): Call trunc_int_for_mode before generating
+	the integer just make sure the constant has been sign extended
+	corectly.
+	(riscv_emit_int_compare): Call trunc_int_for_mode after doing the
+	addition for the new rhs.
+	* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT,
+	then mask off the upper 32bits of the HWI as it will be sign extended.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/constraints.md (DsS): New constraint.
+	(DsD): New constraint.
+	* config/riscv/iterators.md (shiftm1c): New iterator.
+	* config/riscv/bitmanip.md (*bset<mode>_mask):
+	Use shiftm1c.
+	(*bset<mode>_1_mask): Likewise.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/constraints.md (Ds3): New constraint.
+	* config/riscv/predicates.md (imm123_operand): New predicate.
+	* config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
+	(*shNadduw): Likewise.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/riscv.cc (riscv_print_operand):
+	Handle '~'.
+	(riscv_print_operand_punct_valid_p): New function
+	(TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define.
+	* config/riscv/bitmanip.md (<bitmanip_optab>si2/clz_ctz_pcnt):
+	Use %~ instead of conditional the pattern on TARGET_64BIT.
+	(rotrsi3): Likewise.
+	(rotlsi3): Likewise.
+	* config/riscv/riscv.md: Add ~ to the list of modifiers.
+	(addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT.
+	(subsi3): Likewise.
+	(negsi2): Likewise.
+	(mulsi3): Likewise.
+	(optab>si3/any_div): Likewise.
+	(*add<mode>hi3): Likewise.
+	(<optab>si3/any_shift): Likewise.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/riscv.cc (riscv_print_operand): Make a mention to
+	keep the list in riscv.md in sync with this list.
+	* config/riscv/riscv.md: Add list of modifiers as comments.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/sync.md (any_atomic, atomic_optab): Move to ...
+	* config/riscv/iterators.md: Here.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/bitmanip.md
+	(bitmanip_bitwise, bitmanip_minmax, clz_ctz_pcna,
+	tbitmanip_optab, bitmanip_insn, shiftm1): Move to ...
+	* config/riscv/iterators.md: Here.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* config/riscv/riscv.md (GPR): Move to new file.
+	(P, X, BR): Likewise.
+	(MOVE32, MOVE64, SHORT): Likewise.
+	(HISI, SUPERQI, SUBX): Likewise.
+	(ANYI, ANYF, SOFTF): Likewise.
+	(size, load, default_load): Likewise.
+	(softload, store, softstore): Likewise.
+	(reg, fmt, ifmt, amo): Likewise.
+	(UNITMODE, HALFMODE): Likewise.
+	(RINT, rint_pattern, rint_rm): Likewise.
+	(QUIET_COMPARISON, quiet_pattern, QUIET_PATTERN): Likewise.
+	(any_extend, any_shiftrt, any_shift): Likewise.
+	(any_bitwise): Likewise.
+	(any_div, any_mod): Likewise.
+	(any_gt, any_ge, any_lt, any_le): Likewise.
+	(u, su): Likewise.
+	(optab, insn): Likewise.
+	* config/riscv/iterators.md: New file.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106601
+	* config/riscv/bitmanip.md (bswaphi2): New pattern.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106600
+	* config/riscv/bitmanip.md (bswap<mode>2): Remove
+	condition on TARGET_64BIT as X is already conditional there.
+
+2022-08-24  Joseph Myers  <joseph@codesourcery.com>
+
+	* tree.cc (build_real): Give DFP dconst0 the minimum quantum
+	exponent for the type.
+
+2022-08-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	PR target/106733
+	* config/bpf/bpf.cc (bpf_legitimate_address_p): Recognize integer
+	constants as legitimate addresses for functions.
+	(bpf_small_register_classes_for_mode_p): Define target hook.
+
+2022-08-24  Richard Biener  <rguenther@suse.de>
+
+	* gimple-predicate-analysis.cc: Move predicate normalization
+	after the comment documenting it.
+
+2022-08-24  Richard Biener  <rguenther@suse.de>
+
+	* gimple-predicate-analysis.h (predicate): Split out
+	non-predicate related functionality into ..
+	(uninit_analysis): .. this new class.
+	* gimple-predicate-analysis.cc: Refactor into two classes.
+	* tree-ssa-uninit.cc (find_uninit_use): Use uninit_analysis.
+
+2022-08-24  Richard Biener  <rguenther@suse.de>
+
+	* gimple-predicate-analysis.cc (predicate::use_cannot_happen):
+	Do simple_control_dep_chain only up to cd_root, add the PHI
+	operand edge to the chains like init_from_phi_def does.
+	(predicate::is_use_guarded): Speedup early out, avoid half-way
+	initializing the PHI def predicate.
+
+2022-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/106721
+	* config/i386/sse.md (shuffletype): Add V32BF, V16BF and V8BF entries.
+	Change V32HF, V16HF and V8HF entries from "f" to "i".
+	(iptr): Add V32BF, V16BF, V8BF and BF entries.
+	(i128vldq): Add V16HF and V16BF entries.
+	(avx512er_vmrcp28<mode><mask_name><round_saeonly_name>): Fix typo,
+	mask_opernad3 -> mask_operand3.
+
+2022-08-24  Martin Liska  <mliska@suse.cz>
+	    Jørgen Kvalsvik  <j@lambda.is>
+
+	* gcov.cc (add_line_counts): Add group functions to coverage
+	summary.
+	(accumulate_line_counts): Similarly for files.
+
+2022-08-24  Lulu Cheng  <chenglulu@loongson.cn>
+
+	* config/loongarch/genopts/loongarch-strings: Support code model medium.
+	* config/loongarch/genopts/loongarch.opt.in: Likewise.
+	* config/loongarch/loongarch-def.c: Likewise.
+	* config/loongarch/loongarch-def.h (CMODEL_LARGE): Likewise.
+	(CMODEL_EXTREME): Likewise.
+	(N_CMODEL_TYPES): Likewise.
+	(CMODEL_MEDIUM): Likewise.
+	* config/loongarch/loongarch-opts.cc: Likewise.
+	* config/loongarch/loongarch-opts.h (TARGET_CMODEL_MEDIUM): Likewise.
+	* config/loongarch/loongarch-str.h (STR_CMODEL_MEDIUM): Likewise.
+	* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
+	Tls symbol Loading support medium mode.
+	(loongarch_legitimize_call_address): When medium mode, make a symbolic
+	jump with two instructions.
+	(loongarch_option_override_internal): Support medium.
+	* config/loongarch/loongarch.md (@pcalau12i<mode>): New template.
+	(@sibcall_internal_1<mode>): New function call templates added to support
+	medium mode.
+	(@sibcall_value_internal_1<mode>): Likewise.
+	(@sibcall_value_multiple_internal_1<mode>): Likewise.
+	(@call_internal_1<mode>): Likewise.
+	(@call_value_internal_1<mode>): Likewise.
+	(@call_value_multiple_internal_1<mode>): Likewise.
+	* config/loongarch/loongarch.opt: Support medium.
+	* config/loongarch/predicates.md: Add processing about medium mode.
+	* doc/invoke.texi: Document for '-mcmodel=medium'.
+
+2022-08-24  Richard Biener  <rguenther@suse.de>
+
+	* gimple-predicate-analysis.cc (predicate::use_cannot_happen):
+	Start the compute_control_dep_chain walk from the immediate
+	dominator of the PHI.
+
 2022-08-23  H.J. Lu  <hjl.tools@gmail.com>
 
 	PR target/106714
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index a8087bc572d..359f4ea53a5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20220824
+20220825
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 1352a54dbb5..be3e9da8d6f 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2022-08-24  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/103694
+	* simplify.cc (simplify_size): The size expression of an array cannot
+	be simplified if an error occurs while resolving the array spec.
+
 2022-08-22  Harald Anlauf  <anlauf@gmx.de>
 
 	PR fortran/106557
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8f3b3e592cd..3aa57280d45 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,63 @@
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	* lib/target-supports.exp (check_effective_target_bswap):
+	Return true if riscv and ZBB ISA extension is enabled.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106601
+	* gcc.target/riscv/zbb_32_bswap-2.c: New test.
+	* gcc.target/riscv/zbb_bswap-2.c: New test.
+
+2022-08-24  Andrew Pinski  <apinski@marvell.com>
+
+	PR target/106600
+	* gcc.target/riscv/zbb_32_bswap-1.c: New test.
+	* gcc.target/riscv/zbb_bswap-1.c: New test.
+
+2022-08-24  Harald Anlauf  <anlauf@gmx.de>
+
+	PR fortran/103694
+	* gfortran.dg/pr103694.f90: New test.
+
+2022-08-24  Joseph Myers  <joseph@codesourcery.com>
+
+	* gcc.dg/torture/dfp-default-init-1.c,
+	gcc.dg/torture/dfp-default-init-2.c,
+	gcc.dg/torture/dfp-default-init-3.c: New tests.
+
+2022-08-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	PR target/106733
+	* gcc.target/bpf/constant-calls.c: Rename to ...
+	* gcc.target/bpf/constant-calls-1.c: and modify to not expect
+	failure anymore.
+	* gcc.target/bpf/constant-calls-2.c: New test.
+
+2022-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/106721
+	* gcc.target/i386/avx512vl-pr106721.c: New test.
+
+2022-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/106646
+	* g++.dg/cpp/warning-1.C: New test.
+	* g++.dg/cpp/warning-2.C: New test.
+	* g++.dg/cpp/warning-3.C: New test.
+
+2022-08-24  Lulu Cheng  <chenglulu@loongson.cn>
+
+	* gcc.target/loongarch/func-call-medium-1.c: New test.
+	* gcc.target/loongarch/func-call-medium-2.c: New test.
+	* gcc.target/loongarch/func-call-medium-3.c: New test.
+	* gcc.target/loongarch/func-call-medium-4.c: New test.
+	* gcc.target/loongarch/func-call-medium-5.c: New test.
+	* gcc.target/loongarch/func-call-medium-6.c: New test.
+	* gcc.target/loongarch/func-call-medium-7.c: New test.
+	* gcc.target/loongarch/func-call-medium-8.c: New test.
+	* gcc.target/loongarch/tls-gd-noplt.c: Add compile parameter '-mexplicit-relocs'.
+
 2022-08-23  Marek Polacek  <polacek@redhat.com>
 
 	* g++.dg/cpp0x/Wpessimizing-move10.C: New test.
diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog
index 50617857a77..5e3fa0a7725 100644
--- a/libcpp/ChangeLog
+++ b/libcpp/ChangeLog
@@ -1,3 +1,11 @@
+2022-08-24  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/106646
+	* init.cc: Implement C++23 P2437R1 - Support for #warning.
+	(lang_defaults): Set warning_directive for GNUCXX23 and CXX23.
+	* directives.cc (directive_diagnostics): Use different wording of
+	#warning pedwarn for C++.
+
 2022-08-20  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/106645
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index d88ffec6a87..4c78614d1ed 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,60 @@
+2022-08-24  Patrick Palka  <ppalka@redhat.com>
+
+	* include/bits/ranges_algo.h (__min_fn, min): Move to ...
+	* include/bits/ranges_util.h: ... here, in order to avoid
+	including all of ranges_algo.h from <ranges>.
+	* include/std/ranges (__detail::__zip_is_common): Define for
+	C++23 as per P2321R2.
+	(__detail::__tuple_or_pair): Likewise.
+	(__detail::__tuple_or_pair_t): Likewise.
+	(__detail::__tuple_transform): Likewise.
+	(__detail::__tuple_for_each): Likewise.
+	(zip_view): Likewise.
+	(enable_borrowed_range<zip_view>): Likewise.
+	(__detail::__all_random_access): Likewise.
+	(__detail::__all_bidirectional): Likewise.
+	(__detail::__all_forward): Likewise.
+	(__detail::__zip_view_iter_cat): Likewise.
+	(zip_view::_Iterator): Likewise.
+	(zip_view::_Sentinel): Likewise.
+	* testsuite/std/ranges/zip/1.cc: New test.
+
+2022-08-24  Jonathan Wakely  <jwakely@redhat.com>
+
+	Revert:
+	2022-08-24  Will Hawkins  <whh8b@obs.cr>
+
+	* include/bits/basic_string.h (operator+(const string&, const char*)):
+	Remove naive implementation.
+	* include/bits/basic_string.tcc (operator+(const string&, const char*)):
+	Add single-allocation implementation.
+
+2022-08-24  Patrick Palka  <ppalka@redhat.com>
+
+	* include/bits/stl_pair.h (pair::swap const): Add non-standard
+	is_swappable_v constraints.
+	* include/std/tuple (tuple::swap const): Likewise.
+	* testsuite/20_util/tuple/cons/noexcept_specs.cc: Correct some
+	asserts in C++23 mode.
+
+2022-08-24  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/bits/stl_algo.h (__stable_sort): Cast size to
+	iterator's difference type.
+	* testsuite/25_algorithms/stable_sort/4.cc: New test.
+
+2022-08-24  Will Hawkins  <whh8b@obs.cr>
+
+	* include/bits/basic_string.h (operator+(const string&, const char*)):
+	Remove naive implementation.
+	* include/bits/basic_string.tcc (operator+(const string&, const char*)):
+	Add single-allocation implementation.
+
+2022-08-24  Jonathan Wakely  <jwakely@redhat.com>
+
+	* testsuite/20_util/duration_cast/rounding.cc: Check abs with
+	non-reduced duration.
+
 2022-08-23  Patrick Palka  <ppalka@redhat.com>
 
 	* include/bits/stl_bvector.h (_Bit_reference::operator=): Define