From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1643) id EB1D73881D1B; Mon, 13 Feb 2023 13:11:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EB1D73881D1B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676293867; bh=j8ZOtNAr5zN7vhCiMUWGSAHJmyzM2HlN7dIYQvLHLvc=; h=From:To:Subject:Date:From; b=bGWOeKe/hhPuyFS+Doo4SWKUiE35RCC3Z4UFU3TF71xPPjm2YHAKmXbMB0akylwB3 AONQcDyURxouT2Vw8CbSpWZet3+RZMmV8Nwh8qK6NNA5/fszoDKjSZwo0uN8dtLG8n iBHAUaFlruMt+Eu2uTRT+KlyZdhrJGOuj6zCWH4Q= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Thomas Schwinge To: gcc-cvs@gcc.gnu.org, libstdc++-cvs@gcc.gnu.org Subject: [gcc/devel/rust/master] Merge commit '02c031088ac0bbf716aec52e027d615b7a5a572b^' into HEAD X-Act-Checkin: gcc X-Git-Author: Thomas Schwinge X-Git-Refname: refs/heads/devel/rust/master X-Git-Oldrev: 7d39b61800112febb6de6ec8a44f116e48a63baa X-Git-Newrev: 6863cc3a23e8e47b9d8eec31710d5306cafcd65b Message-Id: <20230213131107.EB1D73881D1B@sourceware.org> Date: Mon, 13 Feb 2023 13:11:07 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6863cc3a23e8e47b9d8eec31710d5306cafcd65b commit 6863cc3a23e8e47b9d8eec31710d5306cafcd65b Merge: 7d39b618001 1060cd2ad00 Author: Thomas Schwinge Date: Sun Feb 12 16:29:21 2023 +0100 Merge commit '02c031088ac0bbf716aec52e027d615b7a5a572b^' into HEAD Diff: contrib/ChangeLog | 31 + contrib/gcc-changelog/git_check_commit.py | 6 + contrib/gcc-changelog/git_commit.py | 19 +- contrib/gcc-changelog/git_email.py | 5 +- contrib/gcc-changelog/setup.cfg | 2 +- contrib/gcc-changelog/test_email.py | 18 + contrib/gcc-changelog/test_patches.txt | 121 + gcc/ChangeLog | 104 + gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 5 + gcc/c-family/c-format.cc | 2 +- gcc/c/ChangeLog | 6 + gcc/c/c-parser.cc | 5 + gcc/config.gcc | 23 +- gcc/config/aarch64/aarch64-builtins.cc | 2 +- gcc/config/arm/arm-c.cc | 6 +- gcc/config/gnu-user.h | 3 +- gcc/config/i386/gnu-user-common.h | 2 +- gcc/config/riscv/riscv-passes.def | 1 + gcc/config/riscv/riscv-protos.h | 15 + gcc/config/riscv/riscv-v.cc | 102 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +- gcc/config/riscv/riscv-vector-switch.def | 38 +- gcc/config/riscv/riscv-vsetvl.cc | 2509 ++++++++++++++++++++ gcc/config/riscv/riscv-vsetvl.h | 344 +++ gcc/config/riscv/riscv.cc | 52 +- gcc/config/riscv/t-riscv | 8 + gcc/config/riscv/vector.md | 131 +- gcc/config/rs6000/rs6000-protos.h | 3 + gcc/config/rs6000/rs6000.cc | 102 +- gcc/config/rs6000/rs6000.md | 66 +- gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/cp/ChangeLog | 41 + gcc/cp/constexpr.cc | 2 +- gcc/cp/contracts.cc | 4 +- gcc/cp/cp-gimplify.cc | 57 +- gcc/cp/cp-tree.h | 8 +- gcc/cp/decl.cc | 25 +- gcc/cp/pt.cc | 12 +- gcc/doc/install.texi | 2 + gcc/doc/invoke.texi | 3 +- gcc/fortran/ChangeLog | 5 + gcc/fortran/decl.cc | 8 + gcc/m2/ChangeLog | 22 + gcc/m2/gm2-gcc/m2linemap.cc | 34 +- gcc/m2/gm2-gcc/m2linemap.def | 5 - gcc/m2/gm2-gcc/m2linemap.h | 6 +- gcc/sort.cc | 5 + gcc/testsuite/ChangeLog | 335 +++ gcc/testsuite/c-c++-common/Wsuggest-attribute-1.c | 36 + gcc/testsuite/g++.dg/concepts/auto5.C | 9 + gcc/testsuite/g++.dg/cpp2a/srcloc10.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc11.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc12.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc13.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc3.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc4.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc5.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc6.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc7.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc8.C | 2 +- gcc/testsuite/g++.dg/cpp2a/srcloc9.C | 2 +- gcc/testsuite/g++.dg/modules/pr100881_a.C | 34 + gcc/testsuite/g++.dg/modules/pr100881_b.C | 8 + gcc/testsuite/gcc.dg/c99-complit-2.c | 2 +- gcc/testsuite/gcc.dg/pr108043.c | 12 + gcc/testsuite/gcc.dg/pr108164.c | 19 + gcc/testsuite/gcc.dg/pr64536.c | 8 +- gcc/testsuite/gcc.target/aarch64/acle/pr108140.c | 15 + gcc/testsuite/gcc.target/powerpc/pr103743.c | 52 + gcc/testsuite/gcc.target/powerpc/pr103743_1.c | 95 + gcc/testsuite/gcc.target/powerpc/pr106708.c | 41 + gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 70 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 58 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 58 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 22 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 58 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 46 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 34 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 24 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 18 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 44 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 26 +- .../gcc.target/riscv/rvv/base/vread_csr.c | 13 +- gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 178 +- .../gcc.target/riscv/rvv/base/vwrite_csr.c | 13 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c | 33 + .../riscv/rvv/vsetvl/vlmax_back_prop-1.c | 36 + .../riscv/rvv/vsetvl/vlmax_back_prop-10.c | 59 + .../riscv/rvv/vsetvl/vlmax_back_prop-11.c | 63 + .../riscv/rvv/vsetvl/vlmax_back_prop-12.c | 64 + .../riscv/rvv/vsetvl/vlmax_back_prop-13.c | 64 + .../riscv/rvv/vsetvl/vlmax_back_prop-14.c | 58 + .../riscv/rvv/vsetvl/vlmax_back_prop-15.c | 143 ++ .../riscv/rvv/vsetvl/vlmax_back_prop-16.c | 54 + .../riscv/rvv/vsetvl/vlmax_back_prop-17.c | 59 + .../riscv/rvv/vsetvl/vlmax_back_prop-18.c | 58 + .../riscv/rvv/vsetvl/vlmax_back_prop-19.c | 48 + .../riscv/rvv/vsetvl/vlmax_back_prop-2.c | 50 + .../riscv/rvv/vsetvl/vlmax_back_prop-20.c | 59 + .../riscv/rvv/vsetvl/vlmax_back_prop-21.c | 50 + .../riscv/rvv/vsetvl/vlmax_back_prop-22.c | 58 + .../riscv/rvv/vsetvl/vlmax_back_prop-23.c | 41 + .../riscv/rvv/vsetvl/vlmax_back_prop-24.c | 41 + .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 96 + .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 89 + .../riscv/rvv/vsetvl/vlmax_back_prop-27.c | 51 + .../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 54 + .../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 54 + .../riscv/rvv/vsetvl/vlmax_back_prop-3.c | 47 + .../riscv/rvv/vsetvl/vlmax_back_prop-30.c | 44 + .../riscv/rvv/vsetvl/vlmax_back_prop-31.c | 46 + .../riscv/rvv/vsetvl/vlmax_back_prop-32.c | 46 + .../riscv/rvv/vsetvl/vlmax_back_prop-33.c | 45 + .../riscv/rvv/vsetvl/vlmax_back_prop-34.c | 45 + .../riscv/rvv/vsetvl/vlmax_back_prop-35.c | 38 + .../riscv/rvv/vsetvl/vlmax_back_prop-36.c | 47 + .../riscv/rvv/vsetvl/vlmax_back_prop-37.c | 41 + .../riscv/rvv/vsetvl/vlmax_back_prop-38.c | 73 + .../riscv/rvv/vsetvl/vlmax_back_prop-39.c | 20 + .../riscv/rvv/vsetvl/vlmax_back_prop-4.c | 104 + .../riscv/rvv/vsetvl/vlmax_back_prop-40.c | 22 + .../riscv/rvv/vsetvl/vlmax_back_prop-41.c | 26 + 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