From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2168) id 5633F3858D1E; Tue, 31 Oct 2023 00:17:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5633F3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1698711476; bh=yPONtMIXOazRNFRsdBaEise9e+beEGt++piwrfW3uDc=; h=From:To:Subject:Date:From; b=Q5inXx1hvXJ8Ls1SXO7oupqtsk9w8C8lMpSpxlFJHtc5S5bPAmVl+AsZIiMIH1H+R ad8z1muw+SuViYBM7StuCFEEvvlJBX2jwYVKhzPTszAvGhwW9g1R74uWceVE7xflpp sKJGAmnSu3LJ+fj1W2Upl/j9A4mirozuLQfG7824= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: GCC Administrator To: gcc-cvs@gcc.gnu.org, libstdc++-cvs@gcc.gnu.org Subject: [gcc r14-5022] Daily bump. X-Act-Checkin: gcc X-Git-Author: GCC Administrator X-Git-Refname: refs/heads/master X-Git-Oldrev: 94c0b26f454da642a76c1a7ebbf1475324671bb4 X-Git-Newrev: a5c157b95a4c202ec5b8600f80e7e0c88722e8ad Message-Id: <20231031001756.5633F3858D1E@sourceware.org> Date: Tue, 31 Oct 2023 00:17:56 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a5c157b95a4c202ec5b8600f80e7e0c88722e8ad commit r14-5022-ga5c157b95a4c202ec5b8600f80e7e0c88722e8ad Author: GCC Administrator Date: Tue Oct 31 00:17:32 2023 +0000 Daily bump. Diff: --- fixincludes/ChangeLog | 4 ++ gcc/ChangeLog | 172 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 8 +++ gcc/testsuite/ChangeLog | 64 ++++++++++++++++++ libstdc++-v3/ChangeLog | 11 ++++ 6 files changed, 260 insertions(+), 1 deletion(-) diff --git a/fixincludes/ChangeLog b/fixincludes/ChangeLog index 5b49d8764053..3d5b2d259377 100644 --- a/fixincludes/ChangeLog +++ b/fixincludes/ChangeLog @@ -1,3 +1,7 @@ +2023-10-30 Iain Sandoe + + * configure: Regenerate. + 2023-08-17 Rainer Orth * inclhack.def (darwin_flt_eval_method): Handle macOS 14 guard diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4964796c6a65..fefd8fc06003 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,175 @@ +2023-10-30 Mayshao + + * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize yongfeng. + * common/config/i386/i386-common.cc: Add yongfeng. + * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): + Add ZHAOXIN_FAM7H_YONGFENG. + * config.gcc: Add yongfeng. + * config/i386/driver-i386.cc (host_detect_local_cpu): + Let -march=native recognize yongfeng processors. + * config/i386/i386-c.cc (ix86_target_macros_internal): Add yongfeng. + * config/i386/i386-options.cc (m_YONGFENG): New definition. + (m_ZHAOXIN): Ditto. + * config/i386/i386.h (enum processor_type): Add PROCESSOR_YONGFENG. + * config/i386/i386.md: Add yongfeng. + * config/i386/lujiazui.md: Fix typo. + * config/i386/x86-tune-costs.h (struct processor_costs): + Add yongfeng costs. + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add yongfeng. + (ix86_adjust_cost): Ditto. + * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Replace + m_LUJIAZUI with m_ZHAOXIN. + (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_MOVX): Ditto. + (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. + (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. + (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. + (X86_TUNE_USE_LEAVE): Ditto. + (X86_TUNE_PUSH_MEMORY): Ditto. + (X86_TUNE_LCP_STALL): Ditto. + (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. + (X86_TUNE_OPT_AGU): Ditto. + (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. + (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. + (X86_TUNE_USE_SAHF): Ditto. + (X86_TUNE_USE_BT): Ditto. + (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. + (X86_TUNE_ONE_IF_CONV_INSN): Ditto. + (X86_TUNE_AVOID_MFENCE): Ditto. + (X86_TUNE_EXPAND_ABS): Ditto. + (X86_TUNE_USE_SIMODE_FIOP): Ditto. + (X86_TUNE_USE_FFREEP): Ditto. + (X86_TUNE_EXT_80387_CONSTANTS): Ditto. + (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. + (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. + (X86_TUNE_SSE_TYPELESS_STORES): Ditto. + (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. + (X86_TUNE_USE_GATHER_2PARTS): Add m_YONGFENG. + (X86_TUNE_USE_GATHER_4PARTS): Ditto. + (X86_TUNE_USE_GATHER_8PARTS): Ditto. + (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. + * doc/extend.texi: Add details about yongfeng. + * doc/invoke.texi: Ditto. + * config/i386/yongfeng.md: New file to describe yongfeng processor. + +2023-10-30 Martin Jambor + + PR ipa/111157 + * ipa-prop.h (struct ipa_argagg_value): Newf flag killed. + * ipa-modref.cc (ipcp_argagg_and_kill_overlap_p): New function. + (update_signature): Mark any any IPA-CP aggregate constants at + positions known to be killed as killed. Move check that there is + clone_info after this pruning. + * ipa-cp.cc (ipa_argagg_value_list::dump): Dump the killed flag. + (ipa_argagg_value_list::push_adjusted_values): Clear the new flag. + (push_agg_values_from_plats): Likewise. + (ipa_push_agg_values_from_jfunc): Likewise. + (estimate_local_effects): Likewise. + (push_agg_values_for_index_from_edge): Likewise. + * ipa-prop.cc (write_ipcp_transformation_info): Stream the killed + flag. + (read_ipcp_transformation_info): Likewise. + (ipcp_get_aggregate_const): Update comment, assert that encountered + record does not have killed flag set. + (ipcp_transform_function): Prune all aggregate constants with killed + set. + +2023-10-30 Martin Jambor + + PR ipa/111157 + * ipa-prop.h (ipcp_transformation): New member function template + remove_argaggs_if. + * ipa-sra.cc (zap_useless_ipcp_results): Use remove_argaggs_if to + filter aggreagate constants. + +2023-10-30 Roger Sayle + + PR middle-end/101955 + * config/arc/arc.md (*extvsi_1_0): New define_insn_and_split + to convert sign extract of the least significant bit into an + AND $1 then a NEG when !TARGET_BARREL_SHIFTER. + +2023-10-30 Roger Sayle + + * config/arc/arc.cc (arc_rtx_costs): Improve cost estimates. + Provide reasonable values for SHIFTS and ROTATES by constant + bit counts depending upon TARGET_BARREL_SHIFTER. + (arc_insn_cost): Use insn attributes if the instruction is + recognized. Avoid calling get_attr_length for type "multi", + i.e. define_insn_and_split patterns without explicit type. + Fall-back to set_rtx_cost for single_set and pattern_cost + otherwise. + * config/arc/arc.h (COSTS_N_BYTES): Define helper macro. + (BRANCH_COST): Improve/correct definition. + (LOGICAL_OP_NON_SHORT_CIRCUIT): Preserve previous behavior. + +2023-10-30 Roger Sayle + + * config/arc/arc.cc (arc_split_ashl): Use lsl16 on TARGET_SWAP. + (arc_split_ashr): Use swap and sign-extend on TARGET_SWAP. + (arc_split_lshr): Use lsr16 on TARGET_SWAP. + (arc_split_rotl): Use swap on TARGET_SWAP. + (arc_split_rotr): Likewise. + * config/arc/arc.md (ANY_ROTATE): New code iterator. + (si2_cnt16): New define_insn for alternate form of + swap instruction on TARGET_SWAP. + (ashlsi2_cnt16): Rename from *ashlsi16_cnt16 and move earlier. + (lshrsi2_cnt16): New define_insn for LSR16 instruction. + (*ashlsi2_cnt16): See above. + +2023-10-30 Richard Ball + + * config/arm/aout.h: Change to use the Lrtx label. + * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Remove arm targets + from (!target_pure_code) condition. + (ADDR_VEC_ALIGN): Add align for tables in rodata section. + * config/arm/arm.cc (arm_output_casesi): Alter the function to include + .Lrtx label and remove adr instructions. + * config/arm/arm.md + (arm_casesi_internal): Use force_reg to generate ldr instructions that + would otherwise be out of range, and change rtl to accommodate force reg. + Additionally remove unnecessary register temp. + (casesi): Remove pure code check for Arm. + * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Remove arm + targets from JUMP_TABLES_IN_TEXT_SECTION definition. + +2023-10-30 Jeevitha Palanisamy + + PR target/106907 + * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise + xor to an equality and fix comment indentation. + +2023-10-30 Juzhe-Zhong + + * config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug. + * config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto. + * config/riscv/vector.md: Ditto. + +2023-10-30 liuhongt + + PR target/104610 + * config/i386/i386-expand.cc (ix86_expand_branch): Handle + 512-bit vector with vpcmpeq + kortest. + * config/i386/i386.md (cbranchxi4): New expander. + * config/i386/sse.md: (cbranch4): Extend to V16SImode + and V8DImode. + +2023-10-30 Haochen Gui + + PR target/111449 + * expr.cc (qi_vector_mode_supported_p): Rename to... + (by_pieces_mode_supported_p): ...this, and extends it to do + the checking for both scalar and vector mode. + (widest_fixed_size_mode_for_size): Call + by_pieces_mode_supported_p to examine the mode. + (op_by_pieces_d::smallest_fixed_size_mode_for_size): Likewise. + 2023-10-29 Martin Uecker PR tree-optimization/109334 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index d2cdbe13a4d5..e7de5e82aa57 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20231030 +20231031 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 19da5ba9543a..6eacbeb746e4 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,11 @@ +2023-10-30 Paul Thomas + + PR fortran/104555 + * resolve.cc (resolve_select_type): If the selector expression + has no class component references and the expression is a + derived type, copy the typespec of the symbol to that of the + expression. + 2023-10-27 Harald Anlauf Steven G. Kargl diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5c18129b4ac7..a83adb2d5706 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,67 @@ +2023-10-30 Mayshao + + * g++.target/i386/mv32.C: Handle new -march. + * gcc.target/i386/funcspec-56.inc: Ditto. + +2023-10-30 Martin Jambor + + PR ipa/111157 + * gcc.dg/lto/pr111157_0.c: New test. + * gcc.dg/lto/pr111157_1.c: Second file of the same new test. + +2023-10-30 Patrick O'Neill + + * gcc.target/riscv/rv32i_zcmp.c: Accept any register in the + range of 1-9 for cm.push and cm.popret insns. + +2023-10-30 Roger Sayle + + PR middle-end/101955 + * gcc.target/arc/pr101955.c: New test case. + +2023-10-30 Roger Sayle + + * gcc.target/arc/lsl16-1.c: New test case. + * gcc.target/arc/lsr16-1.c: Likewise. + * gcc.target/arc/swap-1.c: Likewise. + * gcc.target/arc/swap-2.c: Likewise. + +2023-10-30 Richard Ball + + * gcc.target/arm/arm-switchstatement.c: Alter the tests to + change adr instruction to ldr. + +2023-10-30 Francois-Xavier Coudert + + * gcc.target/i386/pr105554.c: Require ifunc. + +2023-10-30 Francois-Xavier Coudert + + * gcc.dg/Wtrampolines.c: Skip on darwin20 and later. + +2023-10-30 Francois-Xavier Coudert + + PR target/112287 + * gcc.target/i386/pr111698.c: Pass -march=sandybridge. + +2023-10-30 Francois-Xavier Coudert + + * gcc.dg/pie-2.c: Skip test on darwin. + +2023-10-30 Richard Biener + + PR testsuite/111462 + * gcc.dg/tree-ssa/ssa-sink-18.c: XFAIL also powerpc64le. + +2023-10-30 Paul Thomas + + PR fortran/104555 + * gfortran.dg/pr104555.f90: New test. + +2023-10-30 liuhongt + + * gcc.target/i386/pr104610-2.c: New test. + 2023-10-29 Iain Buclaw PR d/110712 diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index b350dc265c2c..6548dce335a4 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,14 @@ +2023-10-30 François Dumont + + * config/abi/pre/gnu-versioned-namespace.ver: Add comment on recently + added emul TLS symbols. + +2023-10-30 François Dumont + + * src/experimental/contract.cc + [_GLIBCXX_INLINE_VERSION](handle_contract_violation): Rework comment. + Remove weak attribute. + 2023-10-29 François Dumont * config/abi/pre/gnu-versioned-namespace.ver: Add missing emul TLS