From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cmx-mtlrgo001.bell.net (mta-mtl-005.bell.net [209.71.208.25]) by sourceware.org (Postfix) with ESMTP id 168203858D28 for ; Thu, 5 Jan 2023 18:27:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 168203858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bell.net Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=bell.net X-RG-CM-BuS: 0 X-RG-CM-SC: 0 X-RG-CM: Clean X-Originating-IP: [216.208.213.126] X-RG-Env-Sender: dave.anglin@bell.net X-RG-Rigid: 63B45E0E0054FB02 X-CM-Envelope: MS4xfLC4uVO8iFClV20kMj6thFp0eaN7mw8bx112KQGp9IHFV5WQrFEDLPNdg5+HjsDWkvDXuxGjiNgscp3MvA37KztnaCOrLURrRzOtqT25MVQ+afqtyVNs 3Z/nOcPCqQpGRrqg3LJA1TI/nVggBYqI5yHFFXxbS0NVlbzI49cZiQrcwi69F+IopXg+TbWzMVSWdz2hOi36DSF1HHd0XkIhr0nRPLCmGQ3kbFuVs7IkECJZ mn7PvhckAWiizpC3yYzu6w== X-CM-Analysis: v=2.4 cv=drYdSXs4 c=1 sm=1 tr=0 ts=63b7168d a=+bChh254EysXZpNu6Nt8Zg==:117 a=+bChh254EysXZpNu6Nt8Zg==:17 a=IkcTkHD0fZMA:10 a=mDV3o1hIAAAA:8 a=fa7KhSiFjGH4NGWn5fcA:9 a=QEXdDO2ut3YA:10 a=_FVE-zBwftR9WsbkzFJk:22 Received: from [192.168.2.49] (216.208.213.126) by cmx-mtlrgo001.bell.net (5.8.807) (authenticated as dave.anglin@bell.net) id 63B45E0E0054FB02; Thu, 5 Jan 2023 13:27:25 -0500 Message-ID: <678c81fb-0b62-fc69-7f5d-65bc3a16335a@bell.net> Date: Thu, 5 Jan 2023 13:27:24 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: [committed] hppa: Fix atomic operations on PA-RISC 2.0 processors References: Content-Language: en-US To: libstdc++@gcc.gnu.org From: John David Anglin In-Reply-To: X-Forwarded-Message-Id: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This changes fixes the atomic operations defined for hppa processors in libstdc++-v3. It appears they were originally written with only PA 1.x processors in mind. Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Fix atomic operations on PA-RISC 2.0 processors. PA-RISC 2.0 supports out-of-order execution for loads and stores. Thus, we need to synchonize memory accesses. This change revises the lock releases in __exchange_and_add and __atomic_add to use an ordered store with release semantics. We also use an ordered load in the inner spin loop. We use the "ldcw,co" instruction instead of "ldcw" when compiled for PA 2.0. Most PA 2.0 processors are coherent and can execute the ldcw instruction in cache for improved performance. Finally, the inner spin loop is revised to immediately branch to the ldcw instruction when it detects the lock is free. 2023-01-05 John David Anglin libstdc++-v3/ChangeLog: * config/cpu/hppa/atomicity.h (_PA_LDCW_INSN): Define. (__exchange_and_add): Use _PA_LDCW_INSN. Use ordered store for lock release. Revise loop. (__atomic_add): Likewise. diff --git a/libstdc++-v3/config/cpu/hppa/atomicity.h b/libstdc++-v3/config/cpu/hppa/atomicity.h index bb997e70c1d..658073537a4 100644 --- a/libstdc++-v3/config/cpu/hppa/atomicity.h +++ b/libstdc++-v3/config/cpu/hppa/atomicity.h @@ -25,6 +25,15 @@ #include #include +/* Perform ldcw operation in cache when possible. */ +#ifndef _PA_LDCW_INSN +# ifdef _PA_RISC2_0 +# define _PA_LDCW_INSN "ldcw,co" +# else +# define _PA_LDCW_INSN "ldcw" +# endif +#endif + namespace __gnu_cxx _GLIBCXX_VISIBILITY(default) { _GLIBCXX_BEGIN_NAMESPACE_VERSION @@ -51,19 +60,19 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION int tmp; volatile int& lock = _Atomicity_lock<0>::_S_atomicity_lock; - __asm__ __volatile__ ("ldcw 0(%1),%0\n\t" + __asm__ __volatile__ (_PA_LDCW_INSN " 0(%1),%0\n\t" "cmpib,<>,n 0,%0,.+20\n\t" - "ldw 0(%1),%0\n\t" - "cmpib,= 0,%0,.-4\n\t" + "ldw,ma 0(%1),%0\n\t" + "cmpib,<> 0,%0,.-12\n\t" "nop\n\t" - "b,n .-20" + "b,n .-12" : "=&r" (tmp) : "r" (&lock) : "memory"); result = *__mem; *__mem = result + __val; - __asm__ __volatile__ ("stw %1,0(%0)" + __asm__ __volatile__ ("stw,ma %1,0(%0)" : : "r" (&lock), "r" (tmp) : "memory"); return result; } @@ -75,18 +84,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION int tmp; volatile int& lock = _Atomicity_lock<0>::_S_atomicity_lock; - __asm__ __volatile__ ("ldcw 0(%1),%0\n\t" + __asm__ __volatile__ (_PA_LDCW_INSN " 0(%1),%0\n\t" "cmpib,<>,n 0,%0,.+20\n\t" - "ldw 0(%1),%0\n\t" - "cmpib,= 0,%0,.-4\n\t" + "ldw,ma 0(%1),%0\n\t" + "cmpib,<> 0,%0,.-12\n\t" "nop\n\t" - "b,n .-20" + "b,n .-12" : "=&r" (tmp) : "r" (&lock) : "memory"); *__mem += __val; - __asm__ __volatile__ ("stw %1,0(%0)" + __asm__ __volatile__ ("stw,ma %1,0(%0)" : : "r" (&lock), "r" (tmp) : "memory"); }