From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1921) id 80CDB38618D7; Fri, 24 Jun 2022 05:42:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80CDB38618D7 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Sebastian Huber To: newlib-cvs@sourceware.org Subject: [newlib-cygwin] iflib: Improve mapping of TX/RX queues to CPUs X-Act-Checkin: newlib-cygwin X-Git-Author: Patrick Kelsey X-Git-Refname: refs/heads/master X-Git-Oldrev: fb0a5865e47c31370758bc0bd98f59c9f4b049af X-Git-Newrev: 7c03cdf47e2a664a193a0c97269a353232d3fd8f Message-Id: <20220624054244.80CDB38618D7@sourceware.org> Date: Fri, 24 Jun 2022 05:42:44 +0000 (GMT) X-BeenThere: newlib-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Newlib GIT logs List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Jun 2022 05:42:44 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dnewlib-cygwin.git;h=3D7c03cdf47e2= a664a193a0c97269a353232d3fd8f commit 7c03cdf47e2a664a193a0c97269a353232d3fd8f Author: Patrick Kelsey Date: Mon Apr 26 00:25:59 2021 -0400 iflib: Improve mapping of TX/RX queues to CPUs =20 iflib now supports mapping each (TX,RX) queue pair to the same CPU (default), to separate CPUs, or to a pair of physical and logical CPUs that share the same L2 cache. The mapping mechanism supports unequal numbers of TX and RX queues, with the excess queues always being mapped to consecutive physical CPUs. When the platform cannot distinguish between physical and logical CPUs, all are treated as physical CPUs. See the comment on get_cpuid_for_queue() for the entire matrix. =20 The following device-specific tunables influence the mapping process: dev...iflib.core_offset (existing) dev...iflib.separate_txrx (existing) dev...iflib.use_logical_cores (new) =20 The following new, read-only sysctls provide visibility of the mapping results: dev...iflib.{t,r}xq.cpu =20 When an iflib driver allocates TX softirqs without providing reference RX IRQs, iflib now binds those TX softirqs to CPUs using the above mapping mechanism (that is, treats them as if they were TX IRQs). Previously, such bindings were left up to the grouptaskqueue code and thus fell outside of the iflib CPU mapping strategy. =20 Reviewed by: kbowling Tested by: olivier, pkelsey MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D24094 Diff: --- newlib/libc/sys/rtems/include/sys/cpuset.h | 1 + 1 file changed, 1 insertion(+) diff --git a/newlib/libc/sys/rtems/include/sys/cpuset.h b/newlib/libc/sys/r= tems/include/sys/cpuset.h index 7958e3b1a..a321bddc2 100644 --- a/newlib/libc/sys/rtems/include/sys/cpuset.h +++ b/newlib/libc/sys/rtems/include/sys/cpuset.h @@ -61,6 +61,7 @@ #define CPU_OR_ATOMIC(d, s) BIT_OR_ATOMIC(CPU_SETSIZE, d, s) #define CPU_COPY_STORE_REL(f, t) BIT_COPY_STORE_REL(CPU_SETSIZE, f, t) #define CPU_FFS(p) BIT_FFS(CPU_SETSIZE, p) +#define CPU_FLS(p) BIT_FLS(CPU_SETSIZE, p) #define CPUSET_FSET BITSET_FSET(_NCPUWORDS) #define CPUSET_T_INITIALIZER BITSET_T_INITIALIZER