[newlib-cygwin] arm: Fix the SP used in setting stack limit for standalone application.

[newlib-cygwin] arm: Fix the SP used in setting stack limit for standalone application.

[Richard Earnshaw]

https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=b782dcb2b363974da249c94adedd95d218d89bef

commit b782dcb2b363974da249c94adedd95d218d89bef
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date:   Fri Mar 3 12:45:40 2023 +0000

    arm: Fix the SP used in setting stack limit for standalone application.
    
    Move the instruction that saves SP before the mode check so that
    applications that start in USER mode correctly set the stack limit.

Diff:
---
 libgloss/arm/crt0.S        | 3 +--
 newlib/libc/sys/arm/crt0.S | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S
index 78515180b..79ae1e251 100644
--- a/libgloss/arm/crt0.S
+++ b/libgloss/arm/crt0.S
@@ -149,13 +149,12 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
+	mov	r3, sp /* Save input SP value.  */
 	/* Test mode bits - in User of all are 0.  */
 	tst	r4, #(CPSR_M_MASK)
 	/* "eq" means r4 AND #0x0F is 0.  */
 	beq	.Lskip_cpu_modes
 
-	mov	r3, sp /* Save input SP value.  */
-
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
 	msr	CPSR_c, r1
diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S
index 6b01d8a88..121246cfa 100644
--- a/newlib/libc/sys/arm/crt0.S
+++ b/newlib/libc/sys/arm/crt0.S
@@ -149,13 +149,12 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
+	mov	r3, sp /* Save input SP value.  */
 	/* Test mode bits - in User of all are 0.  */
 	tst	r4, #(CPSR_M_MASK)
 	/* "eq" means r4 AND #0x0F is 0.  */
 	beq	.Lskip_cpu_modes
 
-	mov	r3, sp /* Save input SP value.  */
-
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
 	msr	CPSR_c, r1