From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1035) id 9FA983858CDB; Fri, 3 Mar 2023 13:33:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9FA983858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1677850431; bh=/8vmJvNZWrgpIaPGcMthIkg+PeBD7Z6bSkFASL6QHNg=; h=From:To:Subject:Date:From; b=UQcu5/EMpS+g8n11yTZYEr7DrVdn8kub03HvXYHMJsJGuOvvPm5DjNKqeqJPXn1cK Slyy8KW4xZPXWLlN0WcFYxlKgmjYHN7mjhKkBk7idzvyENDk2yU1ZzPf3u4pCgbZ/w D6svGQ9Rs1jPDbxe5398lNrhalFVa4+6u0J0gAeY= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Earnshaw To: newlib-cvs@sourceware.org Subject: [newlib-cygwin] arm: Fix the SP used in setting stack limit for standalone application. X-Act-Checkin: newlib-cygwin X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/heads/master X-Git-Oldrev: 68db1fa7babf9c9c19b36fa4cf4bb747190c0769 X-Git-Newrev: b782dcb2b363974da249c94adedd95d218d89bef Message-Id: <20230303133351.9FA983858CDB@sourceware.org> Date: Fri, 3 Mar 2023 13:33:51 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dnewlib-cygwin.git;h=3Db782dcb2b36= 3974da249c94adedd95d218d89bef commit b782dcb2b363974da249c94adedd95d218d89bef Author: Srinath Parvathaneni Date: Fri Mar 3 12:45:40 2023 +0000 arm: Fix the SP used in setting stack limit for standalone application. =20 Move the instruction that saves SP before the mode check so that applications that start in USER mode correctly set the stack limit. Diff: --- libgloss/arm/crt0.S | 3 +-- newlib/libc/sys/arm/crt0.S | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index 78515180b..79ae1e251 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -149,13 +149,12 @@ #if (__ARM_ARCH_PROFILE !=3D 'M') /* Following code is compatible for both ARM and Thumb ISA. */ mrs r4, CPSR + mov r3, sp /* Save input SP value. */ /* Test mode bits - in User of all are 0. */ tst r4, #(CPSR_M_MASK) /* "eq" means r4 AND #0x0F is 0. */ beq .Lskip_cpu_modes =20 - mov r3, sp /* Save input SP value. */ - /* FIQ mode, interrupts disabled. */ mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK) msr CPSR_c, r1 diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S index 6b01d8a88..121246cfa 100644 --- a/newlib/libc/sys/arm/crt0.S +++ b/newlib/libc/sys/arm/crt0.S @@ -149,13 +149,12 @@ #if (__ARM_ARCH_PROFILE !=3D 'M') /* Following code is compatible for both ARM and Thumb ISA. */ mrs r4, CPSR + mov r3, sp /* Save input SP value. */ /* Test mode bits - in User of all are 0. */ tst r4, #(CPSR_M_MASK) /* "eq" means r4 AND #0x0F is 0. */ beq .Lskip_cpu_modes =20 - mov r3, sp /* Save input SP value. */ - /* FIQ mode, interrupts disabled. */ mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK) msr CPSR_c, r1