From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1035) id A6FA038582B7; Fri, 3 Mar 2023 13:33:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6FA038582B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1677850436; bh=K7gPk9pc4zv+YsYcHh4jdoXdxfxAkdkWXywvyXe7p5c=; h=From:To:Subject:Date:From; b=uHRrNCWKDtAO3a2isDGbbSY3V3nt0dgeGsjQuLAQv4sMv8HxlxTjTr6IBfpbUHaRI pOoxde2wTZRxkGtCBFZ59fD4tG3GGWqRMzouY7RCNGsyzpuhbyyrPvRHkss4cG9iq5 NcTyYKo4pvuNUbDjDpp8drZinPYErEaikyqxuRLk= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Earnshaw To: newlib-cvs@sourceware.org Subject: [newlib-cygwin] arm: Restrict processor mode change when in hypervisor mode X-Act-Checkin: newlib-cygwin X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/heads/master X-Git-Oldrev: b782dcb2b363974da249c94adedd95d218d89bef X-Git-Newrev: 1d3d2ba54bf7fb7f47510b70cc71489b293ff60d Message-Id: <20230303133356.A6FA038582B7@sourceware.org> Date: Fri, 3 Mar 2023 13:33:56 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dnewlib-cygwin.git;h=3D1d3d2ba54bf= 7fb7f47510b70cc71489b293ff60d commit 1d3d2ba54bf7fb7f47510b70cc71489b293ff60d Author: Srinath Parvathaneni Date: Fri Mar 3 13:12:18 2023 +0000 arm: Restrict processor mode change when in hypervisor mode =20 If a CPU implements EL2 as its highest exception level then programs using newlib may start in hypervisor mode. In that state it is not trivial to switch into the various EL1 modes to configure the individual exception stacks, so do not try. Diff: --- libgloss/arm/crt0.S | 14 +++++++------- newlib/libc/sys/arm/crt0.S | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index 79ae1e251..cd1a20d61 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -122,10 +122,10 @@ * +-----+ <- SP_svc of getting in and out of secure state are no= t as * | | simple as writing to the CPSR mode bits. * | IRQ | -=3D 0x2000 - Mode switch via CPSR is not allowed once in -* | | non-privileged mode, so we take care not to = enter -* ^ +-----+ <- SP_und "User" to set up its SP, and also skip most -* s | | operations if already in that mode. -* t | UND | -=3D 0x1000 +* | | non-privileged mode or in hypervisor mode, s= o we +* ^ +-----+ <- SP_und take care not to enter "User" or "Hypervisor= " mode +* s | | to set up its SP, and also skip most operati= ons if +* t | UND | -=3D 0x1000 already in these modes. * a | | Input parameters: * c +-----+ <- SP_und - sp - Initialized SP * k | | - r2 - May contain SL value from semihosting @@ -150,9 +150,9 @@ /* Following code is compatible for both ARM and Thumb ISA. */ mrs r4, CPSR mov r3, sp /* Save input SP value. */ - /* Test mode bits - in User of all are 0. */ - tst r4, #(CPSR_M_MASK) - /* "eq" means r4 AND #0x0F is 0. */ + ands r1, r4, #(CPSR_M_MASK) + beq .Lskip_cpu_modes + cmp r1, #(CPSR_M_HYP) beq .Lskip_cpu_modes =20 /* FIQ mode, interrupts disabled. */ diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S index 121246cfa..90d5be393 100644 --- a/newlib/libc/sys/arm/crt0.S +++ b/newlib/libc/sys/arm/crt0.S @@ -122,10 +122,10 @@ * +-----+ <- SP_svc of getting in and out of secure state are no= t as * | | simple as writing to the CPSR mode bits. * | IRQ | -=3D 0x2000 - Mode switch via CPSR is not allowed once in -* | | non-privileged mode, so we take care not to = enter -* ^ +-----+ <- SP_und "User" to set up its SP, and also skip most -* s | | operations if already in that mode. -* t | UND | -=3D 0x1000 +* | | non-privileged mode or in hypervisor mode, s= o we +* ^ +-----+ <- SP_und take care not to enter "User" or "Hypervisor= " mode +* s | | to set up its SP, and also skip most operati= ons if +* t | UND | -=3D 0x1000 already in these modes. * a | | Input parameters: * c +-----+ <- SP_und - sp - Initialized SP * k | | - r2 - May contain SL value from semihosting @@ -150,9 +150,9 @@ /* Following code is compatible for both ARM and Thumb ISA. */ mrs r4, CPSR mov r3, sp /* Save input SP value. */ - /* Test mode bits - in User of all are 0. */ - tst r4, #(CPSR_M_MASK) - /* "eq" means r4 AND #0x0F is 0. */ + ands r1, r4, #(CPSR_M_MASK) + beq .Lskip_cpu_modes + cmp r1, #(CPSR_M_HYP) beq .Lskip_cpu_modes =20 /* FIQ mode, interrupts disabled. */