From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2134) id 0AB0D3858C53; Thu, 24 Aug 2023 14:58:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0AB0D3858C53 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1692889088; bh=+GIYw/QLqjX8Kow7qZBkAIs/LWyHod6TRvK5eM/vJrc=; h=From:To:Subject:Date:From; b=CtK1W9dP5gBnQ/gP+lV63jq14clbZSEMlNpwNNS9IyWIo/KO5ONXl73w/pjEzl3R+ qi2W1SPxDimqFI+rLGML7F/xbwPJf7TcC8r08xBFklH7x65m4g0wjV55wjX6O/8Ni0 AKXI+EjobQm8kVEnlEfGdreUvaVokF6WajUrLX3k= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jeff Johnston To: newlib-cvs@sourceware.org Subject: [newlib-cygwin] libgloss: add Xtensa port X-Act-Checkin: newlib-cygwin X-Git-Author: Alexey Lapshin X-Git-Refname: refs/heads/master X-Git-Oldrev: 90d3b16d2b93d573501394d88538c99335edc343 X-Git-Newrev: 42fc2fa37c5995b642d128705cc67316bf9254b7 Message-Id: <20230824145808.0AB0D3858C53@sourceware.org> Date: Thu, 24 Aug 2023 14:58:08 +0000 (GMT) List-Id: https://sourceware.org/git/gitweb.cgi?p=3Dnewlib-cygwin.git;h=3D42fc2fa37c5= 995b642d128705cc67316bf9254b7 commit 42fc2fa37c5995b642d128705cc67316bf9254b7 Author: Alexey Lapshin Date: Wed Aug 9 00:07:04 2023 +0400 libgloss: add Xtensa port =20 Supported esp32 and esp32s2 boards: https://github.com/espressif/esp-toolchain-docs/blob/main/gcc/build-and= -run-native-app.md Diff: --- libgloss/Makefile.am | 3 + libgloss/Makefile.in | 292 ++++++++++++++++++= +++- libgloss/configure | 64 +++++ libgloss/configure.ac | 6 +- libgloss/libnosys/acinclude.m4 | 1 + libgloss/xtensa/Makefile.inc | 55 ++++ libgloss/xtensa/acinclude.m4 | 5 + libgloss/xtensa/app.elf.ld | 190 ++++++++++++++ libgloss/xtensa/board.elf.specs | 5 + libgloss/xtensa/boards/esp32/board.c | 24 ++ libgloss/xtensa/boards/esp32/include/soc/cpu.h | 16 ++ libgloss/xtensa/boards/esp32/include/soc/uart.h | 24 ++ libgloss/xtensa/boards/esp32/memory.elf.ld | 26 ++ libgloss/xtensa/boards/esp32s3/board.c | 24 ++ libgloss/xtensa/boards/esp32s3/include/soc/cpu.h | 16 ++ libgloss/xtensa/boards/esp32s3/include/soc/uart.h | 24 ++ libgloss/xtensa/boards/esp32s3/memory.elf.ld | 21 ++ libgloss/xtensa/crt0.S | 20 ++ libgloss/xtensa/crt1-boards.S | 223 +++++++++++++++++ libgloss/xtensa/crt1-sim.S | 201 +++++++++++++++ libgloss/xtensa/default.specs | 2 + libgloss/xtensa/include/register_access.h | 12 + libgloss/xtensa/include/syscalls.h | 64 +++++ libgloss/xtensa/include/xtensa/corebits.h | 186 ++++++++++++++ libgloss/xtensa/nano.specs | 18 ++ libgloss/xtensa/sim-call.S | 12 + libgloss/xtensa/sim-vectors.S | 186 ++++++++++++++ libgloss/xtensa/sim.elf.specs | 5 + libgloss/xtensa/sleep.S | 69 +++++ libgloss/xtensa/sys.openocd.specs | 8 + libgloss/xtensa/sys.qemu.specs | 8 + libgloss/xtensa/syscalls.c | 205 +++++++++++++++ libgloss/xtensa/window-vectors.S | 252 +++++++++++++++++++ 33 files changed, 2257 insertions(+), 10 deletions(-) diff --git a/libgloss/Makefile.am b/libgloss/Makefile.am index d4b7d4077..f440ad23a 100644 --- a/libgloss/Makefile.am +++ b/libgloss/Makefile.am @@ -103,3 +103,6 @@ endif if CONFIG_WINCE include wince/Makefile.inc endif +if CONFIG_XTENSA +include xtensa/Makefile.inc +endif diff --git a/libgloss/Makefile.in b/libgloss/Makefile.in index 7f46375c0..611b42161 100644 --- a/libgloss/Makefile.in +++ b/libgloss/Makefile.in @@ -190,6 +190,32 @@ check_PROGRAMS =3D $(am__EXEEXT_2) $(am__EXEEXT_3) @CONFIG_RISCV_TRUE@ riscv/libsemihost.a @CONFIG_WINCE_TRUE@am__append_36 =3D $(gdbdir) @CONFIG_WINCE_TRUE@am__append_37 =3D wince/stub.exe +@CONFIG_XTENSA_TRUE@am__append_38 =3D -D_LIBGLOSS -I$(srcdir)/xtensa/inclu= de +@CONFIG_XTENSA_TRUE@am__append_39 =3D \ +@CONFIG_XTENSA_TRUE@ xtensa/default.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/nano.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/sim.elf.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/board.elf.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/sys.qemu.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/sys.openocd.specs \ +@CONFIG_XTENSA_TRUE@ xtensa/crt0.o + +@CONFIG_XTENSA_TRUE@am__append_40 =3D xtensa/libgloss.a +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_41 =3D \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/app.elf.ld \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/crt1-sim.o \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/crt1-boards.o + +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_42 =3D xtensa/l= ibsys_qemu.a \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/libsys_openocd.a +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@am__append_43 =3D xtensa/boards/esp32/memory.elf.ld +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@am__append_44 =3D xtensa/boards/esp32/board.c +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@am__append_45 =3D -I$(srcdir)/xtensa/boards/esp32/include +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@am__append_46 =3D -I$(srcdir)/xtensa/boards/esp32/include +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@am__append_47 =3D xtensa/boards/esp32s3/memory.elf.ld +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@am__append_48 =3D xtensa/boards/esp32s3/board.c +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@am__append_49 =3D -I$(srcdir)/xtensa/boards/esp32s3/include +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@am__append_50 =3D -I$(srcdir)/xtensa/boards/esp32s3/include subdir =3D . ACLOCAL_M4 =3D $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps =3D $(top_srcdir)/../config/depstand.m4 \ @@ -203,7 +229,8 @@ am__aclocal_m4_deps =3D $(top_srcdir)/../config/depstan= d.m4 \ $(top_srcdir)/mcore/acinclude.m4 \ $(top_srcdir)/mips/acinclude.m4 \ $(top_srcdir)/mn10300/acinclude.m4 \ - $(top_srcdir)/moxie/acinclude.m4 $(top_srcdir)/configure.ac + $(top_srcdir)/moxie/acinclude.m4 \ + $(top_srcdir)/xtensa/acinclude.m4 $(top_srcdir)/configure.ac am__configure_deps =3D $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) DIST_COMMON =3D $(srcdir)/Makefile.am $(top_srcdir)/configure \ @@ -515,6 +542,27 @@ riscv_libsemihost_a_LIBADD =3D @CONFIG_RISCV_TRUE@ riscv/riscv_libsemihost_a-semihost-sys_unlink.$(OBJEXT= ) \ @CONFIG_RISCV_TRUE@ riscv/riscv_libsemihost_a-semihost-sys_write.$(OBJEXT) riscv_libsemihost_a_OBJECTS =3D $(am_riscv_libsemihost_a_OBJECTS) +xtensa_libgloss_a_AR =3D $(AR) $(ARFLAGS) +xtensa_libgloss_a_LIBADD =3D +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@am__objects_7 =3D xtensa/boards/esp32/xtensa_libgloss_a-board.$(OBJEXT) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@am__objects_8 =3D xtensa/boards/esp32s3/xtensa_libgloss_a-board.$(OBJ= EXT) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libgloss_a_OBJEC= TS =3D xtensa/xtensa_libgloss_a-sleep.$(OBJEXT) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libgloss_a-= syscalls.$(OBJEXT) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libgloss_a-= window-vectors.$(OBJEXT) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__objects_7) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__objects_8) +xtensa_libgloss_a_OBJECTS =3D $(am_xtensa_libgloss_a_OBJECTS) +xtensa_libsys_openocd_a_AR =3D $(AR) $(ARFLAGS) +xtensa_libsys_openocd_a_LIBADD =3D +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libsys_openocd_a= _OBJECTS =3D xtensa/xtensa_libsys_openocd_a-syscalls.$(OBJEXT) +xtensa_libsys_openocd_a_OBJECTS =3D \ + $(am_xtensa_libsys_openocd_a_OBJECTS) +xtensa_libsys_qemu_a_AR =3D $(AR) $(ARFLAGS) +xtensa_libsys_qemu_a_LIBADD =3D +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libsys_qemu_a_OB= JECTS =3D xtensa/xtensa_libsys_qemu_a-sim-vectors.$(OBJEXT) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libsys_qemu= _a-sim-call.$(OBJEXT) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libsys_qemu= _a-syscalls.$(OBJEXT) +xtensa_libsys_qemu_a_OBJECTS =3D $(am_xtensa_libsys_qemu_a_OBJECTS) @CONFIG_WINCE_TRUE@am__EXEEXT_1 =3D wince/stub.exe$(EXEEXT) @CONFIG_BFIN_TRUE@am__EXEEXT_2 =3D bfin/sim-test$(EXEEXT) @CONFIG_IQ2000_TRUE@am__EXEEXT_3 =3D iq2000/test$(EXEEXT) @@ -575,7 +623,9 @@ SOURCES =3D $(aarch64_librdimon_a_SOURCES) $(arc_libnsi= m_a_SOURCES) \ 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-799,11 +850,13 @@ multilibtool_DATA =3D $(am__append_3) $(am__append_6)= $(am__append_7) \ $(am__append_8) $(am__append_13) $(am__append_15) \ $(am__append_18) $(am__append_22) $(am__append_23) \ $(am__append_27) $(am__append_29) $(am__append_32) \ - $(am__append_34) + $(am__append_34) $(am__append_39) $(am__append_41) \ + $(am__append_43) $(am__append_47) multilibtool_LIBRARIES =3D $(am__append_2) $(am__append_5) \ $(am__append_9) $(am__append_11) $(am__append_20) \ $(am__append_21) $(am__append_24) $(am__append_28) \ - $(am__append_30) $(am__append_33) $(am__append_35) + $(am__append_30) $(am__append_33) $(am__append_35) \ + $(am__append_40) $(am__append_42) includetooldir =3D $(tooldir)/include includetool_DATA =3D $(am__append_16) includesystooldir =3D $(tooldir)/include/sys @@ -1095,6 +1148,27 @@ TEXINFO_TEX =3D ../texinfo/texinfo.tex @CONFIG_WINCE_TRUE@wince_stub_exe_SOURCES =3D wince-stub.c @CONFIG_WINCE_TRUE@wince_stub_exe_CPPFLAGS =3D $(AM_CPPFLAGS) -I$(gdbdir) @CONFIG_WINCE_TRUE@wince_stub_exe_LDADD =3D -lwinsock $(WINCE_STUB_LIBS) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libgloss_a_SOURCES = =3D xtensa/sleep.S \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/window-vectors.S \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_44) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_48) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_qemu_a_CPPFL= AGS =3D -DQEMU_SEMIHOSTING \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_45) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_49) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_qemu_a_SOURC= ES =3D \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sim-vectors.S \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sim-call.S \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c + +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_openocd_a_CP= PFLAGS =3D -DOPENOCD_SEMIHOSTING \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_46) \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_50) +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_openocd_a_SO= URCES =3D \ +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c + +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP= _TRUE@xtensa_libgloss_a_CPPFLAGS =3D -I$(srcdir)/xtensa/boards/esp32s3/incl= ude +@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_T= RUE@xtensa_libgloss_a_CPPFLAGS =3D -I$(srcdir)/xtensa/boards/esp32/include all: config.h $(MAKE) $(AM_MAKEFLAGS) all-recursive =20 @@ -1102,7 +1176,7 @@ all: config.h .SUFFIXES: .S .c .dvi .o .obj .ps am--refresh: Makefile @: -$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_= srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefil= e.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(= srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin= /Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(src= dir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Mak= efile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdi= r)/wince/Makefile.inc $(am__configure_deps) +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_= srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefil= e.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(= srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin= /Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(src= dir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Mak= efile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdi= r)/wince/Makefile.inc $(srcdir)/xtensa/Makefile.inc $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ @@ -1124,7 +1198,7 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/confi= g.status echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfil= es_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_mayb= e);; \ esac; -$(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/= Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile= .inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdi= r)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.in= c $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/l= m32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc = $(srcdir)/wince/Makefile.inc $(am__empty): +$(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/= Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile= .inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdi= r)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.in= c $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/l= m32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc = $(srcdir)/wince/Makefile.inc $(srcdir)/xtensa/Makefile.inc $(am__empty): =20 $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEP= ENDENCIES) $(SHELL) ./config.status --recheck @@ -1782,6 +1856,59 @@ riscv/libsemihost.a: $(riscv_libsemihost_a_OBJECTS) = $(riscv_libsemihost_a_DEPEND $(AM_V_at)-rm -f riscv/libsemihost.a $(AM_V_AR)$(riscv_libsemihost_a_AR) riscv/libsemihost.a $(riscv_libsemiho= st_a_OBJECTS) $(riscv_libsemihost_a_LIBADD) $(AM_V_at)$(RANLIB) riscv/libsemihost.a +xtensa/$(am__dirstamp): + @$(MKDIR_P) xtensa + @: > xtensa/$(am__dirstamp) +xtensa/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) 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xtensa/xtensa_libsys_qemu_a-syscalls.obj `if test -f 'xtensa/= syscalls.c'; then $(CYGPATH_W) 'xtensa/syscalls.c'; else $(CYGPATH_W) '$(sr= cdir)/xtensa/syscalls.c'; fi` + wince_stub_exe-wince-stub.o: wince-stub.c @am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDE= S) $(wince_stub_exe_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT wince_= stub_exe-wince-stub.o -MD -MP -MF $(DEPDIR)/wince_stub_exe-wince-stub.Tpo -= c -o wince_stub_exe-wince-stub.o `test -f 'wince-stub.c' || echo '$(srcdir)= /'`wince-stub.c @am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/wince_stub_exe-wince-st= ub.Tpo $(DEPDIR)/wince_stub_exe-wince-stub.Po @@ -4233,6 +4498,12 @@ distclean-generic: -rm -f riscv/$(DEPDIR)/$(am__dirstamp) -rm -f riscv/$(am__dirstamp) -rm -f wince/$(am__dirstamp) + -rm -f xtensa/$(DEPDIR)/$(am__dirstamp) + -rm -f xtensa/$(am__dirstamp) + -rm -f xtensa/boards/esp32/$(DEPDIR)/$(am__dirstamp) + -rm -f xtensa/boards/esp32/$(am__dirstamp) + -rm -f xtensa/boards/esp32s3/$(DEPDIR)/$(am__dirstamp) + -rm -f xtensa/boards/esp32s3/$(am__dirstamp) =20 maintainer-clean-generic: @echo "This command is intended for maintainers to use" @@ -4245,7 +4516,7 @@ clean-am: clean-aminfo clean-binPROGRAMS clean-checkP= ROGRAMS \ =20 distclean: distclean-recursive -rm -f $(am__CONFIG_DISTCLEAN_FILES) - -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(= DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) l= m32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) + -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(= DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) l= m32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) xtensa/$(DEPDIR) xtensa/board= s/esp32/$(DEPDIR) xtensa/boards/esp32s3/$(DEPDIR) -rm -f Makefile distclean-am: clean-am distclean-compile distclean-generic \ distclean-hdr distclean-local distclean-tags @@ -4388,7 +4659,7 @@ installcheck-am: maintainer-clean: maintainer-clean-recursive -rm -f $(am__CONFIG_DISTCLEAN_FILES) -rm -rf $(top_srcdir)/autom4te.cache - -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(= DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) l= m32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) + -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(= DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) l= m32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) xtensa/$(DEPDIR) xtensa/board= s/esp32/$(DEPDIR) xtensa/boards/esp32s3/$(DEPDIR) -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-aminfo \ maintainer-clean-generic maintainer-clean-local @@ -4537,6 +4808,9 @@ maintainer-clean-local: maintainer-clean-multi @CONFIG_BFIN_TRUE@bfin/basiccrt60xc1.$(OBJEXT): bfin/basiccrt.S @CONFIG_BFIN_TRUE@ $(AM_V_CPPAS)$(CPPASCOMPILE) $(bfin_CPPFLAGS) -o $@ -c = $< $(if $(findstring mcpu=3D,$(CFLAGS)),-mcpu=3Dbf608-any,-mcpu=3Dbf608-non= e) -D__ADSPBF60x_CORE1__ =20 +@CONFIG_XTENSA_TRUE@xtensa/crt0.$(OBJEXT): xtensa/crt0.S +@CONFIG_XTENSA_TRUE@ $(AM_V_CPPAS)$(CPPASCOMPILE) $(CPPFLAGS) -o $@ -c $< + # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: diff --git a/libgloss/configure b/libgloss/configure index c07610411..3c0db8121 100755 --- a/libgloss/configure +++ b/libgloss/configure @@ -589,6 +589,13 @@ LIBOBJS multi_basedir target_makefile_frag_path host_makefile_frag_path +HAVE_XTENSA_BOARD_ESP_FALSE +HAVE_XTENSA_BOARD_ESP_TRUE +HAVE_XTENSA_BOARD_ESP32S3_FALSE +HAVE_XTENSA_BOARD_ESP32S3_TRUE +HAVE_XTENSA_BOARD_ESP32_FALSE +HAVE_XTENSA_BOARD_ESP32_TRUE +XTENSA_BOARD_ESP MOXIE_BUILD_CRT0_FALSE MOXIE_BUILD_CRT0_TRUE MN10300_BSP_LIST @@ -632,6 +639,8 @@ CFLAGS CC NEED_TOP_INCLUDE_DIR_FALSE NEED_TOP_INCLUDE_DIR_TRUE +CONFIG_XTENSA_FALSE +CONFIG_XTENSA_TRUE CONFIG_WINCE_FALSE CONFIG_WINCE_TRUE CONFIG_RISCV_FALSE @@ -2928,6 +2937,9 @@ case "${target}" in =20 subdirs=3D"$subdirs xstormy16" ;; + xtensa-*-*) + config_xtensa=3Dtrue + ;; m32c-*-*) ac_config_files=3D"$ac_config_files m32c/Makefile" =20 @@ -3082,6 +3094,14 @@ else CONFIG_WINCE_FALSE=3D fi =20 + if test x$config_xtensa =3D xtrue; then + CONFIG_XTENSA_TRUE=3D + CONFIG_XTENSA_FALSE=3D'#' +else + CONFIG_XTENSA_TRUE=3D'#' + CONFIG_XTENSA_FALSE=3D +fi + =20 =20 if test x$config_arm =3D xtrue; then @@ -4959,6 +4979,7 @@ case "${target}" in v850*-*-*) ;; w65-*-*) ;; xstormy16-*-*) ;; + xtensa-*-*) ;; z8k-*-*) ;; *) $as_echo "#define MISSING_SYSCALL_NAMES 1" >>confdefs.h @@ -5099,6 +5120,33 @@ esac =20 =20 =20 +XTENSA_BOARD_ESP=3D`echo $CC | sed 's/.*-mdynconfig=3Dxtensa_\(.*\)\.so.*/= \1/;s/.*-mcpu=3D\(^ *\).*/\1/;s/.* .*/unknown/'` + + if test x$XTENSA_BOARD_ESP =3D xesp32; then + HAVE_XTENSA_BOARD_ESP32_TRUE=3D + HAVE_XTENSA_BOARD_ESP32_FALSE=3D'#' +else + HAVE_XTENSA_BOARD_ESP32_TRUE=3D'#' + HAVE_XTENSA_BOARD_ESP32_FALSE=3D +fi + + if test x$XTENSA_BOARD_ESP =3D xesp32s3; then + HAVE_XTENSA_BOARD_ESP32S3_TRUE=3D + HAVE_XTENSA_BOARD_ESP32S3_FALSE=3D'#' +else + HAVE_XTENSA_BOARD_ESP32S3_TRUE=3D'#' + HAVE_XTENSA_BOARD_ESP32S3_FALSE=3D +fi + + if echo $XTENSA_BOARD_ESP | grep -w -e esp32 -e esp32s3 >/dev/null 2>&1; = then + HAVE_XTENSA_BOARD_ESP_TRUE=3D + HAVE_XTENSA_BOARD_ESP_FALSE=3D'#' +else + HAVE_XTENSA_BOARD_ESP_TRUE=3D'#' + HAVE_XTENSA_BOARD_ESP_FALSE=3D +fi + + =20 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for compiler search sett= ings" >&5 $as_echo_n "checking for compiler search settings... " >&6; } @@ -5359,6 +5407,10 @@ if test -z "${CONFIG_WINCE_TRUE}" && test -z "${CONF= IG_WINCE_FALSE}"; then as_fn_error $? "conditional \"CONFIG_WINCE\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${CONFIG_XTENSA_TRUE}" && test -z "${CONFIG_XTENSA_FALSE}"; th= en + as_fn_error $? "conditional \"CONFIG_XTENSA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi if test -z "${NEED_TOP_INCLUDE_DIR_TRUE}" && test -z "${NEED_TOP_INCLUDE_D= IR_FALSE}"; then as_fn_error $? "conditional \"NEED_TOP_INCLUDE_DIR\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -5375,6 +5427,18 @@ if test -z "${am__fastdepCCAS_TRUE}" && test -z "${a= m__fastdepCCAS_FALSE}"; then as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi +if test -z "${HAVE_XTENSA_BOARD_ESP32_TRUE}" && test -z "${HAVE_XTENSA_BOA= RD_ESP32_FALSE}"; then + as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP32\" was never define= d. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAVE_XTENSA_BOARD_ESP32S3_TRUE}" && test -z "${HAVE_XTENSA_B= OARD_ESP32S3_FALSE}"; then + as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP32S3\" was never defi= ned. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAVE_XTENSA_BOARD_ESP_TRUE}" && test -z "${HAVE_XTENSA_BOARD= _ESP_FALSE}"; then + as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi =20 : "${CONFIG_STATUS=3D./config.status}" ac_write_fail=3D0 diff --git a/libgloss/configure.ac b/libgloss/configure.ac index a332193ce..47854eab3 100644 --- a/libgloss/configure.ac +++ b/libgloss/configure.ac @@ -195,6 +195,9 @@ case "${target}" in AC_CONFIG_FILES([xstormy16/Makefile]) subdirs=3D"$subdirs xstormy16" ;; + xtensa-*-*) + config_xtensa=3Dtrue + ;; m32c-*-*) AC_CONFIG_FILES([m32c/Makefile]) subdirs=3D"$subdirs m32c" @@ -248,7 +251,7 @@ AC_SUBST(subdirs) dnl These subdirs have converted to non-recursive make. Hopefully someday= all dnl the ports above will too! m4_foreach_w([SUBDIR], [ - aarch64 arc arm bfin csky d30v iq2000 libnosys lm32 nios2 riscv wince + aarch64 arc arm bfin csky d30v iq2000 libnosys lm32 nios2 riscv wince xt= ensa ], [dnl AM_CONDITIONAL([CONFIG_]m4_toupper(SUBDIR), [test x$config_]SUBDIR =3D x= true) ]) @@ -352,6 +355,7 @@ m4_include([mcore/acinclude.m4]) m4_include([mips/acinclude.m4]) m4_include([mn10300/acinclude.m4]) m4_include([moxie/acinclude.m4]) +m4_include([xtensa/acinclude.m4]) =20 AC_CACHE_CHECK([for compiler search settings], libc_cv_compiler_isystem, [= dnl for subdir in include include-fixed; do diff --git a/libgloss/libnosys/acinclude.m4 b/libgloss/libnosys/acinclude.m4 index 7b0d7b4d6..ba293f08a 100644 --- a/libgloss/libnosys/acinclude.m4 +++ b/libgloss/libnosys/acinclude.m4 @@ -22,6 +22,7 @@ case "${target}" in v850*-*-*) ;; w65-*-*) ;; xstormy16-*-*) ;; + xtensa-*-*) ;; z8k-*-*) ;; *) AC_DEFINE(MISSING_SYSCALL_NAMES, 1, [Missing syscall names]) ;; esac diff --git a/libgloss/xtensa/Makefile.inc b/libgloss/xtensa/Makefile.inc new file mode 100644 index 000000000..02308e4f3 --- /dev/null +++ b/libgloss/xtensa/Makefile.inc @@ -0,0 +1,55 @@ +CPPFLAGS +=3D -D_LIBGLOSS -I$(srcdir)/%D%/include + +multilibtool_DATA +=3D \ + %D%/default.specs \ + %D%/nano.specs \ + %D%/sim.elf.specs \ + %D%/board.elf.specs \ + %D%/sys.qemu.specs \ + %D%/sys.openocd.specs \ + %D%/crt0.o + +multilibtool_LIBRARIES +=3D %D%/libgloss.a + +if HAVE_XTENSA_BOARD_ESP +multilibtool_DATA +=3D \ + %D%/app.elf.ld \ + %D%/crt1-sim.o \ + %D%/crt1-boards.o + +%C%_libgloss_a_SOURCES =3D \ + %D%/sleep.S \ + %D%/syscalls.c \ + %D%/window-vectors.S + +multilibtool_LIBRARIES +=3D %D%/libsys_qemu.a +%C%_libsys_qemu_a_CPPFLAGS =3D -DQEMU_SEMIHOSTING +%C%_libsys_qemu_a_SOURCES =3D \ + %D%/sim-vectors.S \ + %D%/sim-call.S \ + %D%/syscalls.c + +multilibtool_LIBRARIES +=3D %D%/libsys_openocd.a +%C%_libsys_openocd_a_CPPFLAGS =3D -DOPENOCD_SEMIHOSTING +%C%_libsys_openocd_a_SOURCES =3D \ + %D%/syscalls.c + +if HAVE_XTENSA_BOARD_ESP32 +multilibtool_DATA +=3D %D%/boards/esp32/memory.elf.ld +%C%_libgloss_a_SOURCES +=3D %D%/boards/esp32/board.c +%C%_libgloss_a_CPPFLAGS =3D -I$(srcdir)/%D%/boards/esp32/include +%C%_libsys_qemu_a_CPPFLAGS +=3D -I$(srcdir)/%D%/boards/esp32/include +%C%_libsys_openocd_a_CPPFLAGS +=3D -I$(srcdir)/%D%/boards/esp32/include +endif + +if HAVE_XTENSA_BOARD_ESP32S3 +multilibtool_DATA +=3D %D%/boards/esp32s3/memory.elf.ld +%C%_libgloss_a_SOURCES +=3D %D%/boards/esp32s3/board.c +%C%_libgloss_a_CPPFLAGS =3D -I$(srcdir)/%D%/boards/esp32s3/include +%C%_libsys_qemu_a_CPPFLAGS +=3D -I$(srcdir)/%D%/boards/esp32s3/include +%C%_libsys_openocd_a_CPPFLAGS +=3D -I$(srcdir)/%D%/boards/esp32s3/include +endif +endif + +%D%/crt0.$(OBJEXT): %D%/crt0.S + $(AM_V_CPPAS)$(CPPASCOMPILE) $(CPPFLAGS) -o $@ -c $< diff --git a/libgloss/xtensa/acinclude.m4 b/libgloss/xtensa/acinclude.m4 new file mode 100644 index 000000000..fc98f8a3d --- /dev/null +++ b/libgloss/xtensa/acinclude.m4 @@ -0,0 +1,5 @@ +XTENSA_BOARD_ESP=3D`echo $CC | sed 's/.*-mdynconfig=3Dxtensa_\(.*\)\.so.*/= \1/;s/.*-mcpu=3D\(^ *\).*/\1/;s/.* .*/unknown/'` +AC_SUBST([XTENSA_BOARD_ESP]) +AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP32], [test x$XTENSA_BOARD_ESP =3D xes= p32]) +AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP32S3], [test x$XTENSA_BOARD_ESP =3D x= esp32s3]) +AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP], [echo $XTENSA_BOARD_ESP | grep -w = -e esp32 -e esp32s3 >/dev/null 2>&1]) diff --git a/libgloss/xtensa/app.elf.ld b/libgloss/xtensa/app.elf.ld new file mode 100644 index 000000000..12c7eb8ab --- /dev/null +++ b/libgloss/xtensa/app.elf.ld @@ -0,0 +1,190 @@ +__stack =3D ORIGIN(dram_seg) + LENGTH(dram_seg); +__MIN_STACK_SIZE =3D 0x1000; + +ENTRY(_start) +SECTIONS +{ + . =3D SEGMENT_START("iram_seg", 0); + .vectors : + { + _vector_table =3D ABSOLUTE(.); + . =3D 0x0; + KEEP(*(.WindowVectors.text)); + . =3D 0x180; + KEEP(*(.Level2InterruptVector.text)); + . =3D 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . =3D 0x200; + KEEP(*(.Level4InterruptVector.text)); + . =3D 0x240; + KEEP(*(.Level5InterruptVector.text)); + . =3D 0x280; + KEEP(*(.DebugExceptionVector.text)); + . =3D 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . =3D 0x300; + KEEP(*(.KernelExceptionVector.text)); + . =3D 0x340; + KEEP(*(.UserExceptionVector.text)); + . =3D 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . =3D 0x400; + KEEP(*(.ResetVector.text)); + *(.*Vector.literal) + . =3D ALIGN (16); + } > iram_seg + + text : + { + KEEP (*(.init.literal)) + KEEP (*(SORT_NONE(.init))) + *(.literal .text .stub .literal.* .text.* .gnu.linkonce.literal.* .gnu= .linkonce.t.*.literal .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + KEEP (*(.fini.literal)) + KEEP (*(SORT_NONE(.fini))) + } > iram_seg + + PROVIDE (__etext =3D .); + PROVIDE (_etext =3D .); + PROVIDE (etext =3D .); + + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . =3D ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (= CONSTANT (MAXPAGESIZE) - 1)); . =3D DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESI= ZE), CONSTANT (COMMONPAGESIZE)); + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start =3D .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end =3D .); + } + .init_array : + { + PROVIDE_HIDDEN (__init_array_start =3D .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ct= ors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *= crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end =3D .); + } + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start =3D .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dt= ors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *= crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end =3D .); + } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + _data_start =3D .; + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + *(.data1) + } + _edata =3D .; PROVIDE (edata =3D .); + . =3D .; + __bss_start =3D .; + .bss : + { + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. + FIXME: Why do we need it? When there is no .bss section, we do not + pad the .data section. */ + . =3D ALIGN(. !=3D 0 ? 32 / 8 : 1); + } + . =3D ALIGN(32 / 8); + . =3D ALIGN(32 / 8); + _end =3D .; PROVIDE (end =3D .); + . =3D DATA_SEGMENT_END (.); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(. <=3D __stack - __MIN_STACK_SIZE, "region DRAM overflowed by .da= ta and .bss sections") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.= *) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + .debug_addr 0 : { *(.debug_addr) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} + diff --git a/libgloss/xtensa/board.elf.specs b/libgloss/xtensa/board.elf.sp= ecs new file mode 100644 index 000000000..87cff19e7 --- /dev/null +++ b/libgloss/xtensa/board.elf.specs @@ -0,0 +1,5 @@ +*startfile: +crt1-boards%O%s + +*lib: +-lc --whole-archive -lgloss --no-whole-archive -lpthread_stubs -lc %Tmemor= y.elf.ld %Tapp.elf.ld diff --git a/libgloss/xtensa/boards/esp32/board.c b/libgloss/xtensa/boards/= esp32/board.c new file mode 100644 index 000000000..f5c73e533 --- /dev/null +++ b/libgloss/xtensa/boards/esp32/board.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include + +void board_init(void) +{ + WRITE_REGISTER(UART0_CLKDIV_REG, UART0_CLKDIV_VAL); +} + +void board_uart_write_char(char c) +{ + /* wait until txfifo_cnt =3D=3D 0 */ + while (UART0_TXFIFO_CNT) { + ; + } + if (c =3D=3D '\n') { + WRITE_REGISTER(UART0_TX_ADDR, '\r'); + } + WRITE_REGISTER(UART0_TX_ADDR, c); +} diff --git a/libgloss/xtensa/boards/esp32/include/soc/cpu.h b/libgloss/xten= sa/boards/esp32/include/soc/cpu.h new file mode 100644 index 000000000..4a16fb236 --- /dev/null +++ b/libgloss/xtensa/boards/esp32/include/soc/cpu.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef SOC_CPU_H +#define SOC_CPU_H + +/* + * ESP32 starts with CPU frequency 40MHz + * Let's do not reconfigure it to simplify libgloss + */ +#define CPU_FREQUENCY_MHZ 40 +#define CPU_FREQUENCY_HZ (CPU_FREQUENCY_MHZ * 1000000) + +#endif // SOC_CPU_H diff --git a/libgloss/xtensa/boards/esp32/include/soc/uart.h b/libgloss/xte= nsa/boards/esp32/include/soc/uart.h new file mode 100644 index 000000000..c7b7eb281 --- /dev/null +++ b/libgloss/xtensa/boards/esp32/include/soc/uart.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef SOC_UART_H +#define SOC_UART_H + +#include +#include + +#define UART0_BAUDRATE 115200 + +#define UART0_TX_ADDR 0x60000000 +#define UART0_BASE 0x3ff40000 +#define UART0_CLKDIV_REG (UART0_BASE + 0x14) +#define UART0_STATUS (UART0_BASE + 0x1c) +#define UART0_CLKDIV_VAL (CPU_FREQUENCY_HZ / UART0_BAUDRATE ) +#define UART0_TXFIFO_CNT (((READ_REGISTER(UART0_STATUS)) >> 16) & 0xff) + + +void board_uart_write_char(char c); + +#endif // SOC_UART_H diff --git a/libgloss/xtensa/boards/esp32/memory.elf.ld b/libgloss/xtensa/b= oards/esp32/memory.elf.ld new file mode 100644 index 000000000..fa0e423b5 --- /dev/null +++ b/libgloss/xtensa/boards/esp32/memory.elf.ld @@ -0,0 +1,26 @@ +/* + * IROM/DRAM definition in QEMU: + * [ESP32_MEMREGION_IROM] =3D { 0x40000000, 0x70000 }, + * [ESP32_MEMREGION_DRAM] =3D { 0x3ffae000, 0x52000 }, + * + * In theory we could use whole DRAM section, but I had some faults when u= sing + * memory in range 0x3ffae000 - 0x3ffb0000 + * + * But used memory range for data such as esp-idf for ESP32 to satisfy use= r's + * expectation on chip emulation + * + * Pass '--defsym=3Dentire_dram_seg=3D1' to linker script to use whole DRAM + * + */ + +MEMORY +{ + iram_seg (X) : org =3D 0x40078000, len =3D 0x28000 +/* 64k at the end of DRAM, after ROM bootloader stack + * or entire DRAM (for QEMU only) + */ + dram_seg (RW) : org =3D DEFINED(entire_dram_seg) ? 0x3FFB0000 : 0x3FFF00= 00, + len =3D DEFINED(entire_dram_seg) ? 0x50000 : 0x10000 +} + + diff --git a/libgloss/xtensa/boards/esp32s3/board.c b/libgloss/xtensa/board= s/esp32s3/board.c new file mode 100644 index 000000000..f5c73e533 --- /dev/null +++ b/libgloss/xtensa/boards/esp32s3/board.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include + +void board_init(void) +{ + WRITE_REGISTER(UART0_CLKDIV_REG, UART0_CLKDIV_VAL); +} + +void board_uart_write_char(char c) +{ + /* wait until txfifo_cnt =3D=3D 0 */ + while (UART0_TXFIFO_CNT) { + ; + } + if (c =3D=3D '\n') { + WRITE_REGISTER(UART0_TX_ADDR, '\r'); + } + WRITE_REGISTER(UART0_TX_ADDR, c); +} diff --git a/libgloss/xtensa/boards/esp32s3/include/soc/cpu.h b/libgloss/xt= ensa/boards/esp32s3/include/soc/cpu.h new file mode 100644 index 000000000..2210ba7b0 --- /dev/null +++ b/libgloss/xtensa/boards/esp32s3/include/soc/cpu.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef SOC_CPU_H +#define SOC_CPU_H + +/* + * ESP32S3 starts with CPU frequency 40MHz + * Let's do not reconfigure it to simplify libgloss + */ +#define CPU_FREQUENCY_MHZ 40 +#define CPU_FREQUENCY_HZ (CPU_FREQUENCY_MHZ * 1000000) + +#endif // SOC_CPU_H diff --git a/libgloss/xtensa/boards/esp32s3/include/soc/uart.h b/libgloss/x= tensa/boards/esp32s3/include/soc/uart.h new file mode 100644 index 000000000..c6241fdec --- /dev/null +++ b/libgloss/xtensa/boards/esp32s3/include/soc/uart.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef SOC_UART_H +#define SOC_UART_H + +#include +#include + +#define UART0_BAUDRATE 115200 + +#define UART0_TX_ADDR 0x60000000 +#define UART0_BASE 0x60000000 +#define UART0_CLKDIV_REG (UART0_BASE + 0x14) +#define UART0_STATUS (UART0_BASE + 0x1c) +#define UART0_CLKDIV_VAL (CPU_FREQUENCY_HZ / UART0_BAUDRATE ) +#define UART0_TXFIFO_CNT (((READ_REGISTER(UART0_STATUS)) >> 16) & 0x3ff) + + +void board_uart_write_char(char c); + +#endif // SOC_UART_H diff --git a/libgloss/xtensa/boards/esp32s3/memory.elf.ld b/libgloss/xtensa= /boards/esp32s3/memory.elf.ld new file mode 100644 index 000000000..6426b7fc6 --- /dev/null +++ b/libgloss/xtensa/boards/esp32s3/memory.elf.ld @@ -0,0 +1,21 @@ +/* + * IROM/DRAM definition in QEMU: + * [ESP32S3_MEMREGION_IROM] =3D { 0x40000000, 0x60000 }, + * [ESP32S3_MEMREGION_DRAM] =3D { 0x3FC80000, 0x70000 }, + * + * In theory we could use whole DRAM section, but I had some faults when u= sing + * memory in range 0x3ffae000 - 0x3ffb0000 + * + * But used memory range for data such as esp-idf for ESP32S3 to satisfy u= ser's + * expectation on chip emulation + * + * Pass '--defsym=3Dentire_dram_seg=3D1' to linker script to use whole DRAM + * + */ + +MEMORY +{ + iram_seg (X) : org =3D 0x40378000, len =3D 0x70000 + dram_seg (RW) : org =3D DEFINED(entire_dram_seg) ? 0x3FC80000 : 0x3FCF00= 00, + len =3D DEFINED(entire_dram_seg) ? 0x70000 : 0x10000 +} diff --git a/libgloss/xtensa/crt0.S b/libgloss/xtensa/crt0.S new file mode 100644 index 000000000..67c359c5b --- /dev/null +++ b/libgloss/xtensa/crt0.S @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +/* crt0.S + * Dummy startup file which calls main() function. + * It can be used for compilation tests only. + */ + + .text + + /* + * Simple jump to main(). + */ + + .global _start + _start: + movi a4, main + jx a4 /* jump to main */ diff --git a/libgloss/xtensa/crt1-boards.S b/libgloss/xtensa/crt1-boards.S new file mode 100644 index 000000000..a703634af --- /dev/null +++ b/libgloss/xtensa/crt1-boards.S @@ -0,0 +1,223 @@ +// crt1-boards.S +// +// For most hardware / boards, this code sets up the C calling context +// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start +// which sets up the C library, calls constructors and registers destructo= rs, +// and calls main(). +// +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2013 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// board_init board-specific (uart/mingloss/tinygloss.c) +// xthal_dcache_all_writeback from HAL library +// __stack from linker script (see LSP Ref Manual) +// __bss_start from linker script (see LSP Ref Manual) +// _end from linker script (see LSP Ref Manual) + +.type main, @function + +# define CALL call4 +# define CALLX callx4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ + + +/*************************************************************************= */ + + .text + .align 4 +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // + + movi a0, 0 // keep this register zero. + + wsr a0, INTENABLE // INTENABLE value is not defined after reset. + //make sure that interrupts are shut off (*before* we lower PS.INTLEVE= L and PS.EXCM!) + + // Windowed register init, so we can call windowed code (eg. C code). + movi a1, 1 + wsr a1, WINDOWSTART + // The processor always clears WINDOWBASE at reset, so no need to clear = it here. + // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0). + // However, assuming hard reset is not yet always practical, so do this = anyway: + wsr a0, WINDOWBASE + rsync + + // Set VECBASE to use our vectors instead vectors in ROM + movi a1, _vector_table + wsr a1, VECBASE + + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4 (or zero), the stack frame for _start can be empty. + + movi sp, __stack + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, enable window exceptions if app= licable). + */ + movi a3, PS_UM|PS_WOE + wsr a3, PS + rsync + + + /* + * Do any initialization that affects the memory map, such as + * setting up TLB entries, that needs to be done before we can + * successfully clear BSS (e.g. if some BSS segments are in + * remapped areas). + * + * NOTE: This hook works where the reset vector does not unpack + * segments (see "ROM packing" in the LSP manual), or where + * unpacking of segments is not affected by memory remapping. + * If ROM unpacking is affected, TLB setup must be done in + * assembler from the reset vector. + * + * The __memmap_init() routine can be a C function, however it + * does not have BSS initialized! In particular, __memmap_init() + * cannot set BSS variables, i.e. uninitialized global variables + * (they'll be wiped out by the following BSS clear), nor can it + * assume they are yet initialized to zero. + * + * The __memmap_init() function is optional. It is marked as a + * weak symbol, so that it gets valued zero if not defined. + */ + .weak __memmap_init + movi a4, __memmap_init + beqz a4, 1f + CALLX a4 +1: + + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * + */ + movi a6, __bss_start + movi a8, _end + sub a8, a8, a6 + movi a7, 0 + CALL memset + + /* init semihosting if has function */ + .weak __semihosting_init + movi a4, __semihosting_init + beqz a4, 2f + CALLX a4 +2: + + // We can now call C code, the C calling environment has been initialize= d. + // + // From this point on, we use ABI-specific macros to refer to registers = a0 .. a15 + // (ARG#). + + + .type board_init, @function + .type __clibrary_init, @function + .type exit, @function + + + // Initialize the board (eg. UART, etc). + CALL board_init + + /* + * Call __clibrary_init to initialize the C library: + * + * void __clibrary_init(int argc, char ** argv, char ** environ, + * void(*init_func)(void), void(*fini_func)(void)); + */ + + // Pass an empty argv array, with an empty string as the program name. + + .weak _init + .weak _fini + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv =3D ["", 0] + movi ARG3, _start_envp // envp =3D [0] + movi ARG4, _init // function that calls constructors + movi ARG5, _fini // function that calls destructors + l32i ARG1, ARG1, 0 // argc =3D 1 + CALL __clibrary_init + + // Call: int main(int argc, char ** argv, char ** environ); + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv =3D ["", 0] + movi ARG3, _start_envp // envp =3D [0] + l32i ARG1, ARG1, 0 // argc =3D 1 + CALL main + // The return value is the same register as the first outgoing argument. + CALL exit // exit with main's return value + // Does not return here. + + .data + // Mark argc/argv/envp parameters as weak so that an external + // object file can override them. + .weak _start_argc, _start_argv, _start_envp + .align 4 +_start_argv: + .word _start_null // empty program name +_start_null: +_start_envp: + .word 0 // end of argv array, empty string, empty environ +_start_argc: + .word 1 // one argument (program name) + .text + + .size _start, . - _start + diff --git a/libgloss/xtensa/crt1-sim.S b/libgloss/xtensa/crt1-sim.S new file mode 100644 index 000000000..4f9924c3b --- /dev/null +++ b/libgloss/xtensa/crt1-sim.S @@ -0,0 +1,201 @@ +// crt1-sim.S +// For the Xtensa simulator target, this code sets up the C calling context +// and calls main() (via __clibrary_start). +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2012 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// __stack from linker script (see LSP Ref Manual) + +.type __clibrary_init, @function +.type main, @function +.type exit, @function + +# define CALL call4 +# define CALLX callx4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ + + .data + .weak _start_envp // allow overriding + .align 4 +_start_envp: .word 0 // empty environ + + .text + .align 4 + +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // + movi a0, 0 // keep this register zero. + + wsr a0, INTENABLE // INTENABLE value is not defined after reset. + //make sure that interrupts are shut off (*before* we lower PS.INTLEVE= L and PS.EXCM!) + + // Windowed register init, so we can call windowed code (eg. C code). + movi a1, 1 + wsr a1, WINDOWSTART + // The processor always clears WINDOWBASE at reset, so no need to clear = it here. + // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0). + // However, assuming hard reset is not yet always practical, so do this = anyway: + wsr a0, WINDOWBASE + rsync + + // Set VECBASE to use our vectors instead vectors in ROM + movi a1, _vector_table + wsr a1, VECBASE + + + // Run only one core + // Multi-threading could be supported in future + rsr.prid a1 // core and multiprocessor ID + extui a1, a1, 13, 1 // extract core ID + beqz a1, .Lcore0 // goto Lcore0 for core0 only +.Lsuspend: // other cores are suspended + waiti 0 + j .Lsuspend + +.Lcore0: + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4, the stack frame for _start can be empty. + movi sp, __stack + + // reserve stack space for + // - argv array + // - argument strings + movi a2, SYS_argv_size + simcall // returns size of argv[] + its strings in a2 + + // The stack only needs 16-byte alignment. + // However, here we round up the argv size further to 128 byte multiples + // so that in most cases, variations in argv[0]'s path do not result in + // different stack allocation. Otherwise, such variations can impact + // execution timing (eg. due to cache effects etc) for the same code and = data. + // If we have a PIF, it's more likely the extra required space is okay. + addi a2, a2, 127 + srli a2, a2, 7 + slli a2, a2, 7 + + // No need to use MOVSP because we have no caller (we're the + // base caller); in fact it's better not to use MOVSP in this + // context, to avoid unnecessary ALLOCA exceptions and copying + // from undefined memory: + // sub a3, sp, a2 + // movsp sp, a3 + sub sp, sp, a2 + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, enable window exceptions if app= licable). + */ + movi a3, PS_UM|PS_WOE // PS.WOE =3D 1, PS.UM =3D 1, PS.EXCM =3D 0, PS.INT= LEVEL =3D 0 + wsr a3, PS + rsync + + #if XCHAL_HAVE_FP || XCHAL_HAVE_DFP + movi a3, 1 + wsr a3, CPENABLE + #endif + +1: + + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * For speed, we clear memory using an ISS simcall + * (see crt1-boards.S for more generic BSS clearing code). + */ + movi a6, __bss_start + movi a7, _end + bgeu a6, a7, .Lnobss +.Lbssloop: + movi a2, SYS_memset + l32i a3, a6, 0 // arg1 =3D fill start address + movi a4, 0 // arg2 =3D fill pattern + l32i a5, a6, 4 // get end address + addi a6, a6, 8 // next bss table entry + sub a5, a5, a3 // arg3 =3D fill size in bytes + simcall // memset(a3,a4,a5) + bltu a6, a7, .Lbssloop // loop until end of bss table +.Lnobss: + + mov a3, sp // tell simcall where to write argv[] + movi a2, SYS_argv + simcall // write argv[] array at a3 + + movi a2, SYS_argc + simcall // put argc in a2 + + .weak _init + .weak _fini + mov ARG2, sp // argv + movi ARG3, _start_envp // envp + movi ARG4, _init // _init + movi ARG5, _fini // _fini + CALL __clibrary_init + + mov ARG1, a2 // argc + mov ARG2, sp // argv + CALL main + + // The return value is the same register as the first outgoing argument. + CALL exit // exit with main's return value + // Does not return here. + + .size _start, . - _start + diff --git a/libgloss/xtensa/default.specs b/libgloss/xtensa/default.specs new file mode 100644 index 000000000..6002fe450 --- /dev/null +++ b/libgloss/xtensa/default.specs @@ -0,0 +1,2 @@ +*lib: +-lc -lnosys -lc diff --git a/libgloss/xtensa/include/register_access.h b/libgloss/xtensa/in= clude/register_access.h new file mode 100644 index 000000000..517220481 --- /dev/null +++ b/libgloss/xtensa/include/register_access.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef REGISTER_ACCESS_H +#define REGISTER_ACCESS_H + +#define WRITE_REGISTER(addr, val) (*((volatile uint32_t *)(addr))) =3D (ui= nt32_t)(val) +#define READ_REGISTER(addr) (*((volatile uint32_t *)(addr))) + +#endif // REGISTER_ACCESS_H diff --git a/libgloss/xtensa/include/syscalls.h b/libgloss/xtensa/include/s= yscalls.h new file mode 100644 index 000000000..323d6fa35 --- /dev/null +++ b/libgloss/xtensa/include/syscalls.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef XTENSA_SIMCALL_H +#define XTENSA_SIMCALL_H + +#ifdef OPENOCD_SEMIHOSTING +/* This data based on libgloss project (file aarch64/svc.h) */ + +#define ESP_SEMIHOSTING_SYS_DRV_INFO 0x100 +#define ADP_STOPPED_APPLICATION_EXIT 0x20026 + +#define SYS_close 0x02 +#define SYS_clock 0x10 +#define SYS_elapsed 0x30 +#define SYS_errno 0x13 +#define SYS_exit 0x18 +#define SYS_exit_extended 0x20 +#define SYS_flen 0x0C +#define SYS_get_cmdline 0x15 +#define SYS_heapinfo 0x16 +#define SYS_iserror 0x08 +#define SYS_istty 0x09 +#define SYS_open 0x01 +#define SYS_read 0x06 +#define SYS_readc 0x07 +#define SYS_remove 0x0E +#define SYS_rename 0x0F +#define SYS_lseek 0x0A +#define SYS_system 0x12 +#define SYS_tickfreq 0x31 +#define SYS_time 0x11 +#define SYS_tmpnam 0x0D +#define SYS_write 0x05 +#define SYS_writec 0x03 +#define SYS_write0 0x04 + +#else + +/* This data based on QEMU project (file target/xtensa/xtensa-semi.c) */ + +#define SYS_exit 1 +#define SYS_read 3 +#define SYS_write 4 +#define SYS_open 5 +#define SYS_close 6 +#define SYS_lseek 19 +#define SYS_select_one 29 +#define SYS_sendto 27 +#define SYS_recvfrom 28 +#define SYS_select_one 29 +#define SYS_bind 30 +#define SYS_ioctl 31 + +#define SYS_argc 1000 +#define SYS_argv_size 1001 +#define SYS_argv 1002 +#define SYS_memset 1004 + +#endif /* OPENOCD_SEMIHOSTING */ + +#endif /* !XTENSA_SIMCALL_H */ diff --git a/libgloss/xtensa/include/xtensa/corebits.h b/libgloss/xtensa/in= clude/xtensa/corebits.h new file mode 100644 index 000000000..445e33495 --- /dev/null +++ b/libgloss/xtensa/include/xtensa/corebits.h @@ -0,0 +1,186 @@ +/* + * xtensa/corebits.h - Xtensa Special Register field positions, masks, val= ues. + * + * (In previous releases, these were defined in specreg.h, a generated fil= e. + * This file is not generated, ie. it is processor configuration independ= ent.) + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */ + +/* + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_COREBITS_H +#define XTENSA_COREBITS_H + +/* EXCCAUSE register fields: */ +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3F +/* EXCCAUSE register values: */ +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, depreca= ted, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, depre= cated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, depr= ecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) = for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not i= mplemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10..11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetc= h (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Sto= re (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction F= etch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or = Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw ref= ill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries= match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction= Fetch */ +/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Ins= truction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw ref= ill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries= match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or= Store */ +/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load= */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Sto= re */ +/* Reserved 30..31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' whe= n disabled */ +#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled= */ +#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled= */ +#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled= */ +#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled= */ +#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled= */ +#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled= */ +#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled= */ +#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled= */ +/* Reserved 40..63 */ + +/* PS register fields: */ +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK +#define PS_WOE_ABI PS_WOE_MASK +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)< +#include + +//#define PS_OWB_SHIFT 8 +//#define PS_OWB_BITS 4 +//#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction= ) for alloca */ + +#if XCHAL_HAVE_L32R + .section .rodata +_sim_panic_msg: + .ascii "PANIC: Unhandled exception!\n" + _sim_panic_msg_len =3D . - _sim_panic_msg + + .section .text + .literal .Lpanic_msg, _sim_panic_msg + .literal .Lpanic_msg_len, _sim_panic_msg_len + .align 4 +_xt_unhandled_exc: + movi a2, SYS_write + movi a3, 2 + l32r a4, .Lpanic_msg + l32r a5, .Lpanic_msg_len + simcall +#else +_xt_unhandled_exc: +#endif + movi a2, SYS_exit + movi a3, 1 + simcall + +/* +--------------------------------------------------------------------------= ------ +Handle alloca exception generated by interruptee executing 'movsp'. +This uses space between the window vectors, so is essentially "free". +All interruptee's regs are intact except a0 which is saved in EXCSAVE_1, +and PS.EXCM has been set by the exception hardware (can't be interrupted). +The fact the alloca exception was taken means the registers associated with +the base-save area have been spilled and will be restored by the underflow +handler, so those 4 registers are available for scratch. +The code is optimized to avoid unaligned branches and minimize cache misse= s. +--------------------------------------------------------------------------= ------ +*/ + + #if XCHAL_HAVE_WINDOWED + .section .text + .global _xt_alloca_exc + .align 4 +_xt_alloca_exc: + + rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratc= h */ + rsr a2, PS + extui a3, a2, 8/*PS_OWB_BITS*/, 4/*PS_OWB_BITS*/ + xor a3, a3, a4 /* bits changed from old to current windowbase= */ + rsr a4, EXCSAVE1 /* restore original a0 (now in a4) */ + slli a3, a3, 8 + xor a2, a2, a3 /* flip changed bits in old window base */ + wsr a2, PS /* update PS.OWB to new window base */ + rsync + + bbci.l a4, 31, _WindowUnderflow4 + rotw -1 /* original a0 goes to a8 */ + bbci.l a8, 30, _WindowUnderflow8 + rotw -1 + j _WindowUnderflow12 + #endif + + +/* +--------------------------------------------------------------------------= ------ + User exception handler. +--------------------------------------------------------------------------= ------ +*/ + + #if XCHAL_HAVE_WINDOWED + .section .text + .align 4 +_xt_to_alloca_exc: + j _xt_alloca_exc /* in window vectors section */ + #endif + + .type _xt_user_exc,@function + .align 4 +_xt_user_exc: + + rsr a0, EXCCAUSE + /* Handle alloca and syscall exceptions */ + #if XCHAL_HAVE_WINDOWED + beqi a0, 5/*EXCCAUSE_ALLOCA*/, _xt_to_alloca_exc + #endif + j _xt_unhandled_exc + + +/* +--------------------------------------------------------------------------= ------ +NMI Exception +--------------------------------------------------------------------------= ------ +*/ + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + .global NMIExceptionVector + .type NMIExceptionVector,@function + .align 4 + +NMIExceptionVector: + j _xt_unhandled_exc + + .end literal_prefix + +/* +--------------------------------------------------------------------------= ------ +Kernel Exception +--------------------------------------------------------------------------= ------ +*/ + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + .global KernelExceptionVector + .type KernelExceptionVector,@function + .align 4 + +KernelExceptionVector: + j _xt_unhandled_exc + + .end literal_prefix + +/* +--------------------------------------------------------------------------= ------ +User Exception +--------------------------------------------------------------------------= ------ +*/ + + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector + .type _UserExceptionVector,@function + .align 4 + +_UserExceptionVector: + + wsr a0, EXCSAVE1 /* preserve a0 */ + j _xt_user_exc /* user exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +/* +----------------------------------------------[...] [diff truncated at 100000 bytes]