diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S
index 78515180bf06f1da37669e4c7e6608c76e1b096d..9d1b649864b1c920b2c1bab7b6b069d52d708c53 100644
--- a/libgloss/arm/crt0.S
+++ b/libgloss/arm/crt0.S
@@ -122,10 +122,10 @@
 *   +-----+ <- SP_svc         of getting in and out of secure state are not as
 *   |     |                   simple as writing to the CPSR mode bits.
 *   | IRQ | -= 0x2000       - Mode switch via CPSR is not allowed once in
-*   |     |                   non-privileged mode, so we take care not to enter
-* ^ +-----+ <- SP_und         "User" to set up its SP, and also skip most
-* s |     |                   operations if already in that mode.
-* t | UND | -= 0x1000
+*   |     |                   non-privileged mode or in hypervisor mode, so we
+* ^ +-----+ <- SP_und         take care not to enter "User" or "Hypervisor" mode
+* s |     |                   to set up its SP, and also skip most operations if
+* t | UND | -= 0x1000         already in these modes.
 * a |     |                Input parameters:
 * c +-----+ <- SP_und       - sp - Initialized SP
 * k |     |                 - r2 - May contain SL value from semihosting
@@ -149,12 +149,11 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
-	/* Test mode bits - in User of all are 0.  */
-	tst	r4, #(CPSR_M_MASK)
-	/* "eq" means r4 AND #0x0F is 0.  */
+	mov	r3, sp
+	ands	r1, r4, #(CPSR_M_MASK)
+	beq	.Lskip_cpu_modes
+	cmp	r1, #(CPSR_M_HYP)
 	beq	.Lskip_cpu_modes
-
-	mov	r3, sp /* Save input SP value.  */
 
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)
diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S
index 6b01d8a88b77f44b1ba495aa1f69156f12749527..582cd789897b8a2239581618462047155b55d166 100644
--- a/newlib/libc/sys/arm/crt0.S
+++ b/newlib/libc/sys/arm/crt0.S
@@ -122,10 +122,10 @@
 *   +-----+ <- SP_svc         of getting in and out of secure state are not as
 *   |     |                   simple as writing to the CPSR mode bits.
 *   | IRQ | -= 0x2000       - Mode switch via CPSR is not allowed once in
-*   |     |                   non-privileged mode, so we take care not to enter
-* ^ +-----+ <- SP_und         "User" to set up its SP, and also skip most
-* s |     |                   operations if already in that mode.
-* t | UND | -= 0x1000
+*   |     |                   non-privileged mode or in hypervisor mode, so we
+* ^ +-----+ <- SP_und         take care not to enter "User" or "Hypervisor" mode
+* s |     |                   to set up its SP, and also skip most operations if
+* t | UND | -= 0x1000         already in these modes.
 * a |     |                Input parameters:
 * c +-----+ <- SP_und       - sp - Initialized SP
 * k |     |                 - r2 - May contain SL value from semihosting
@@ -149,12 +149,11 @@
 #if (__ARM_ARCH_PROFILE != 'M')
 	/* Following code is compatible for both ARM and Thumb ISA.  */
 	mrs	r4, CPSR
-	/* Test mode bits - in User of all are 0.  */
-	tst	r4, #(CPSR_M_MASK)
-	/* "eq" means r4 AND #0x0F is 0.  */
+	mov	r3, sp
+	ands	r1, r4, #(CPSR_M_MASK)
+	beq	.Lskip_cpu_modes
+	cmp	r1, #(CPSR_M_HYP)
 	beq	.Lskip_cpu_modes
-
-	mov	r3, sp /* Save input SP value.  */
 
 	/* FIQ mode, interrupts disabled.  */
 	mov	r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK)