From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 041723858D33 for ; Thu, 2 Mar 2023 13:05:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 041723858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 046AB1FB; Thu, 2 Mar 2023 05:06:08 -0800 (PST) Received: from [10.2.78.76] (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 16F8C3F587; Thu, 2 Mar 2023 05:05:23 -0800 (PST) Message-ID: <409759de-41a3-2f52-e7d3-f74582f59efe@foss.arm.com> Date: Thu, 2 Mar 2023 13:05:22 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2][Newlib] arm: Restrict processor mode change when in hypervisor mode. Content-Language: en-GB To: Srinath Parvathaneni , newlib@sourceware.org Cc: Richard Earnshaw , nd References: <33476d31-2d9d-3aee-cd60-7f70e256e3dd@arm.com> From: Richard Earnshaw In-Reply-To: <33476d31-2d9d-3aee-cd60-7f70e256e3dd@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3488.0 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 23/02/2023 17:10, Srinath Parvathaneni wrote: > Hi All, > > In _stack_init function of crt0.S file, when the current mode is not > user mode, > all the processor modes are parsed and the corresponding stack limit are > set for > these modes for all A-profile and R-profile CPU's. But when the current > processor > mode is hypervisor mode, changing to any other mode using CPSR will > result in an > illegal instruction as per Arm-arm and simulator throws undefined > instruction > exception. The reference to a simulator here is confusing. You might have found this on one, but it's a reflection of the way the architecture is specified and not specific to running under simulation. > This patch prevent the change of hypervisor mode to any other mode in > _stack_init > function in crt0.S files. > > Regression tested on arm-none-eabi target for newlib and newlib-nano and > found > no regressions. > > Ok for newlib master? > > Regards, > Srinath. > > libgloss/ChangeLog: > > 2023-02-23  Srinath Parvathaneni  > >         * arm/crt0.S (_stack_init): Add check for hypervisor mode. > > newlib/ChangeLog: > > 2023-02-23  Srinath Parvathaneni  > >         * libc/sys/arm/crt0.S (_stack_init): Add check for hypervisor > mode. - /* Test mode bits - in User of all are 0. */ - tst r4, #(CPSR_M_MASK) - /* "eq" means r4 AND #0x0F is 0. */ + mov r3, sp + ands r1, r4, #(CPSR_M_MASK) + beq .Lskip_cpu_modes + cmp r1, #(CPSR_M_HYP) You don't mention anywhere why you've moved the instruction that copies SP into R3 before the user-mode check. I think it's probably right, but I think really that's a separate issue that deserves a separate patch (even though it's pretty trivial). So please can you resend as two patches, the first fixing the SP->r3 copy and the second for the hypervisor mode issue. R.