From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 28CB83B0FADB for ; Mon, 19 Dec 2022 10:09:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 28CB83B0FADB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A906A1042; Mon, 19 Dec 2022 02:09:44 -0800 (PST) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53BBB3F7B4; Mon, 19 Dec 2022 02:09:03 -0800 (PST) Message-ID: <7ca62fc8-618e-e213-92c1-195a9b55da1c@foss.arm.com> Date: Mon, 19 Dec 2022 10:08:46 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH] libgloss: arm: break newlib dependency To: Mike Frysinger , newlib@sourceware.org References: <20221214091304.25170-1-vapier@gentoo.org> Content-Language: en-GB From: Richard Earnshaw In-Reply-To: <20221214091304.25170-1-vapier@gentoo.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3496.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 14/12/2022 09:13, Mike Frysinger wrote: > The libgloss port has been reaching back into newlib internals for a > single header whose contents have been frozen for almost a decade. > To break this backwards libgloss->newlib dependency, duplicate that > header here so we can keep libgloss independent as it's meant to be. This isn't really 'newlib internals', it's a header file that tries to provide ACLE[1] compatibility for older versions of GCC that lacked such support. Having two copies of this is a maintenance burden, so I'm not entirely sure this is a great thing to do, even if the copies are supposed to be identical. If we can agree on a common location in the source tree that both newlib and libgloss can pull this from, then I'm happy to move it if that would make you happier. R. [1] https://arm-software.github.io/acle/main/ > --- > libgloss/arm/Makefile.in | 2 - > libgloss/arm/acle-compat.h | 182 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 182 insertions(+), 2 deletions(-) > create mode 100644 libgloss/arm/acle-compat.h > > diff --git a/libgloss/arm/Makefile.in b/libgloss/arm/Makefile.in > index 06fae10c1fca..d0d5ea89d62e 100644 > --- a/libgloss/arm/Makefile.in > +++ b/libgloss/arm/Makefile.in > @@ -97,8 +97,6 @@ IQ80310_INSTALL = install-iq80310 > # Host specific makefile fragment comes in here. > @host_makefile_frag@ > > -INCLUDES += `if [ -d ${objroot}/newlib ]; then echo -I$(srcroot)/newlib/libc/machine/arm; fi` > - > # > # build a test program for each target board. Just trying to get > # it to link is a good test, so we ignore all the errors for now. > diff --git a/libgloss/arm/acle-compat.h b/libgloss/arm/acle-compat.h > new file mode 100644 > index 000000000000..888ae2ea8afb > --- /dev/null > +++ b/libgloss/arm/acle-compat.h > @@ -0,0 +1,182 @@ > +/* > + * Copyright (c) 2014 ARM Ltd > + * All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions > + * are met: > + * 1. Redistributions of source code must retain the above copyright > + * notice, this list of conditions and the following disclaimer. > + * 2. Redistributions in binary form must reproduce the above copyright > + * notice, this list of conditions and the following disclaimer in the > + * documentation and/or other materials provided with the distribution. > + * 3. The name of the company may not be used to endorse or promote > + * products derived from this software without specific prior written > + * permission. > + * > + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. > + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED > + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR > + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF > + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING > + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#ifndef __ARM_ARCH > + > +/* ACLE standardises a set of pre-defines that describe the ARM architecture. > + These were mostly implemented in GCC around GCC-4.8; older versions > + have no, or only partial support. To provide a level of backwards > + compatibility we try to work out what the definitions should be, given > + the older pre-defines that GCC did produce. This isn't complete, but > + it should be enough for use by routines that depend on this header. */ > + > +/* No need to handle ARMv8, GCC had ACLE support before that. */ > + > +# ifdef __ARM_ARCH_7__ > +/* The common subset of ARMv7 in all profiles. */ > +# define __ARM_ARCH 7 > +# define __ARM_ARCH_ISA_THUMB 2 > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_LDREX 7 > +# define __ARM_FEATURE_UNALIGNED > +# endif > + > +# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) > +# define __ARM_ARCH 7 > +# define __ARM_ARCH_ISA_THUMB 2 > +# define __ARM_ARCH_ISA_ARM > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_SIMD32 > +# define __ARM_FEATURE_DSP > +# define __ARM_FEATURE_QBIT > +# define __ARM_FEATURE_SAT > +# define __ARM_FEATURE_LDREX 15 > +# define __ARM_FEATURE_UNALIGNED > +# ifdef __ARM_ARCH_7A__ > +# define __ARM_ARCH_PROFILE 'A' > +# else > +# define __ARM_ARCH_PROFILE 'R' > +# endif > +# endif > + > +# ifdef __ARM_ARCH_7EM__ > +# define __ARM_ARCH 7 > +# define __ARM_ARCH_ISA_THUMB 2 > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_SIMD32 > +# define __ARM_FEATURE_DSP > +# define __ARM_FEATURE_QBIT > +# define __ARM_FEATURE_SAT > +# define __ARM_FEATURE_LDREX 7 > +# define __ARM_FEATURE_UNALIGNED > +# define __ARM_ARCH_PROFILE 'M' > +# endif > + > +# ifdef __ARM_ARCH_7M__ > +# define __ARM_ARCH 7 > +# define __ARM_ARCH_ISA_THUMB 2 > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_QBIT > +# define __ARM_FEATURE_SAT > +# define __ARM_FEATURE_LDREX 7 > +# define __ARM_FEATURE_UNALIGNED > +# define __ARM_ARCH_PROFILE 'M' > +# endif > + > +# ifdef __ARM_ARCH_6T2__ > +# define __ARM_ARCH 6 > +# define __ARM_ARCH_ISA_THUMB 2 > +# define __ARM_ARCH_ISA_ARM > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_SIMD32 > +# define __ARM_FEATURE_DSP > +# define __ARM_FEATURE_QBIT > +# define __ARM_FEATURE_SAT > +# define __ARM_FEATURE_LDREX 4 > +# define __ARM_FEATURE_UNALIGNED > +# endif > + > +# ifdef __ARM_ARCH_6M__ > +# define __ARM_ARCH 6 > +# define __ARM_ARCH_ISA_THUMB 1 > +# define __ARM_ARCH_PROFILE 'M' > +# endif > + > +# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \ > + || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \ > + || defined (__ARM_ARCH_6ZK__) > +# define __ARM_ARCH 6 > +# define __ARM_ARCH_ISA_THUMB 1 > +# define __ARM_ARCH_ISA_ARM > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_SIMD32 > +# define __ARM_FEATURE_DSP > +# define __ARM_FEATURE_QBIT > +# define __ARM_FEATURE_SAT > +# define __ARM_FEATURE_UNALIGNED > +# ifndef __thumb__ > +# if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__) > +# define __ARM_FEATURE_LDREX 15 > +# else > +# define __ARM_FEATURE_LDREX 4 > +# endif > +# endif > +# endif > + > +# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__) > +# define __ARM_ARCH 5 > +# define __ARM_ARCH_ISA_ARM > +# ifdef __ARM_ARCH_5TE__ > +# define __ARM_ARCH_ISA_THUMB 1 > +# endif > +# define __ARM_FEATURE_CLZ > +# define __ARM_FEATURE_DSP > +# endif > + > +# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__) > +# define __ARM_ARCH 5 > +# define __ARM_ARCH_ISA_ARM > +# ifdef __ARM_ARCH_5TE__ > +# define __ARM_ARCH_ISA_THUMB 1 > +# endif > +# define __ARM_FEATURE_CLZ > +# endif > + > +# ifdef __ARM_ARCH_4T__ > +# define __ARM_ARCH 4 > +# define __ARM_ARCH_ISA_ARM > +# define __ARM_ARCH_ISA_THUMB 1 > +# endif > + > +# ifdef __ARM_ARCH_4__ > +# define __ARM_ARCH 4 > +# define __ARM_ARCH_ISA_ARM > +# endif > + > +# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__) > +# define __ARM_ARCH 3 > +# define __ARM_ARCH_ISA_ARM > +# endif > + > +# ifdef __ARM_ARCH_2__ > +# define __ARM_ARCH 2 > +# define __ARM_ARCH_ISA_ARM > +# endif > + > +# ifdef __ARMEB__ > +# define __ARM_BIG_ENDIAN > +# endif > + > +/* If we still don't know what the target architecture is, then we're > + probably not using GCC. */ > +# ifndef __ARM_ARCH > +# error Unable to determine architecture version. > +# endif > + > +#endif /* __ARM_ARCH */ > +