From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 54488384242B for ; Thu, 26 Nov 2020 19:02:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 54488384242B Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFC2D1478; Thu, 26 Nov 2020 11:02:54 -0800 (PST) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C57B3F23F; Thu, 26 Nov 2020 11:02:54 -0800 (PST) Subject: Re: AArch64 ILP32 strcmp bug To: Keith Packard , Joel Sherrill Cc: "newlib@sourceware.org" References: <58625577-97a0-80eb-2d1f-626d5f89abf9@foss.arm.com> <87pn40vu44.fsf@keithp.com> From: Richard Earnshaw Message-ID: <875238d8-613c-2d8e-6498-df1ead351b99@foss.arm.com> Date: Thu, 26 Nov 2020 19:02:45 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <87pn40vu44.fsf@keithp.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3498.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, NICE_REPLY_A, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Nov 2020 19:02:56 -0000 On 26/11/2020 18:41, Keith Packard wrote: > Joel Sherrill via Newlib writes: > >> In the meantime, would you think a patch to disable the optimized >> method when ilp32 is appropriate for newlib? There is still the risk of >> other methods having bugs. The alternative I see is to completely >> PREFER_SIZE_OVER_SPEED for aarch64 and disable all of the >> aarch64 assembly which seems worse. > > There's also setjmp/longjmp, which are only available in assembly form. > > Here's a completely untested patch (I'm afraid I don't have an ilp32 > aarch64 compiler available today) which may help with that: > > diff --git a/newlib/libc/machine/aarch64/setjmp.S b/newlib/libc/machine/aarch64/setjmp.S > index 0856145bf..df94eebd1 100644 > --- a/newlib/libc/machine/aarch64/setjmp.S > +++ b/newlib/libc/machine/aarch64/setjmp.S > @@ -45,6 +45,9 @@ > .global setjmp > .type setjmp, %function > setjmp: > +#ifndef __LP64__ > + mov w0, w0 > +#endif > mov x16, sp > #define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS] > #define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS] > @@ -60,6 +63,10 @@ setjmp: > .global longjmp > .type longjmp, %function > longjmp: > +#ifndef __LP64__ > + mov w0, w0 > +#endif > + > #define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS] > #define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS] > GPR_LAYOUT > AFAICT gcc doesn't define __LP64__, so I don't think this will work; it's also backwards - you shouldn't assume that because __LP64__ isn't defined that we have a 32-bit pointer. GCC does, however, define __ILP32__ when building for that ABI. The right way to do this is to create a new header file, machine/aarch64/machine/asm.h, which contains a gas macro called, lets say `ptr_param', that takes the *number* of register argument and is then conditionally defined to either nothing or an assembly statement that narrows the register with that number. In the main function code you can then write simply ptr_param 0 and avoid all conditional assembly in the main source files. R.