From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 20E733855022 for ; Wed, 7 Jul 2021 00:29:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 20E733855022 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x52a.google.com with SMTP id y40so1018083ede.4 for ; Tue, 06 Jul 2021 17:29:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6cQhkIr9VGMaJ2shB0dXDoWlF3SKcm6rWzOPkd6q9+w=; b=cmDboYT8XZBnDC5D4aUlbfUU0D61oRCsbgcTgcvDHqzTjLf5t7v+Sa5o5TtFyLJB4C c2zbLbohDtpz2w7NcdRih/vRSTDwyqkwb5FxR+cXfYmkfk3b3rvuzVgZy4nIrWqir5mZ vbKo319iCjGk0YI/eSAOqN0CoNyWp0EEYMUrW54U6IL45ggBMFKAbrURCL/fA+UqWL0+ vhSnz51gtlSUSS6Y5SmCKzpplrUOkKn52znyPc16zIH3zRtkc098rtFNy7EDo2N417JN 8VaFbVRNpI2hwfKWYu+Xknr27kgX3lnz599h4TKfNvSQcUYYF5Kd0T8n6L9MD+0MearS ttTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6cQhkIr9VGMaJ2shB0dXDoWlF3SKcm6rWzOPkd6q9+w=; b=Qa37/kiRpc4xxLL6PPbeM+l50WHicYWYKDyURJBo00jFTx0z3qoC94T1sSUE/eYIgq +1H8wqBLpgzaQTo95f2CeYk5bvLTv9IM6xgFaY/TfjK0382uWc2HbF5JImlbx+EvUTIM PVwHxi2/+lMpijJcF6InEupnI/KmoeQAqjxlt6Cp+7cCa83c1his769gavE9BNQily6L 0c0oPsLeBjT72+ABzHdjxgEOGxMozcAh/TkJmEwq5NWKxpqzwa7gttOzDzMTagdGRAVb 9IozwTOSg2CAlnjBdbO8uZuyb3KIYcuvnObn6W24J4HGn+INgCGzW0CnBjCwmTQxFJY0 +yew== X-Gm-Message-State: AOAM532LZc5hqdBkIPx1yon7u5O4OVFPgXtJOg8O4fF+1ndHb1l6tDzA Keg/x/po/vGrLzoU9ntzyY7nLFK7+hXLuUOKpiA= X-Google-Smtp-Source: ABdhPJx73bJ8nYDwp593YhniziNK4auJWP6dUk0BEwgGB9ZiL1+JUBKd686t90V3kF5bYAOExRMz2KXFODd2JjSXcEY= X-Received: by 2002:aa7:d982:: with SMTP id u2mr25934808eds.230.1625617751110; Tue, 06 Jul 2021 17:29:11 -0700 (PDT) MIME-Version: 1.0 References: <9F9C0A22-1CCA-47F8-8C19-F44ED4B47A8F@comcast.net> In-Reply-To: <9F9C0A22-1CCA-47F8-8C19-F44ED4B47A8F@comcast.net> From: ElijaxApps Date: Wed, 7 Jul 2021 02:29:00 +0200 Message-ID: Subject: Re: Help porting newlib to a new CPU architecture (sorta) To: Paul Koning Cc: Newlib X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Jul 2021 00:29:14 -0000 Hi *@Paul*, I am looking at the code you maintain. I downloaded Eclipse for C / C ++ and I am currently cloning gcc repository. My intention is to read carefully your code and rewrite the less possible. Also I have looked up that internals gcc manual mentioned above, and it is really all I need to read now. I am very thankful to you, It is really recomfortating to find out the very right person to ask for help. Really appreciate it. I have not had time yet to check yet avr, h8, m6809 codes, but seems also candidate alternatives, so, I will note below the characteristics of my architecture, in depth, to help us decide which one is closer to mine. *4x8b GP Registers*- A, Accumulator, Argc - B, Summand, Auxiliar in indirections for higher 8 bit addressing - C, Auxiliar, Auxiliar used in indirections for mid 8 bit addressing, String register (not connected to ALU but it is connected to other REGS via bus) - D, Auxiliar, Auxiliar used in indirections for lower 8 bit addressing. *Memory Address Registers*Those point to RAM for in/redirections and look ups into RAM. - M0 lower 8 bit - M1 mid 8 bit - M2 high 8 bit * M2 + M1 + M0 conforms a full 24 bit address. *Stack registers:*- SR0 stores M0 on push while calling a new branch. Pops to M0 on return. Allows REG B to be pushed.- - SR1 stores M1 on push while calling a new branch. Pops to M1 on return. Allows REG C to be pushed. - SR2 stores M1 on push while calling a new branch. Pops to M2 on return. Allows REG D to be pushed. *Output register*- Stores temporarily one char to be output. It will be replaced by a text based GPU with 64K of memory to allow cursor operations on the lcd and also speed up printing, with a separate independant clock. *Flags Register* - Carry flag - Zero flag - Parity flag (not yet shown not used) - Borrow flag ('' '' '' '' '') *So It's basically an automat, with stack, with 8 bit ALU, with 4 GP registers, with 24bit addressable memory, and 24bit max length push/pop item.* 1) Let's decide the appropiate basis first. 2) As a side part, I am able now I read the code, to better understand how gcc relates to gas, and, now I am able to understand also how would it be to just, "make gcc to spit my pseudoassy" and just use my assembler. Knowing this is possible, I will apart the idea for the moment as plab - B to the purpose of compiling existing C / C ++ 8 bit software into Libre 8, with at least GCC. (This is good at least, and very very much easier :)) ). Now I am interested into use the full chain, including gas, with the "internals" manual provided. If everything fails or I got overwhelmed, I got plan B. Thank you all, Elijax Apps. El mi=C3=A9, 7 jul 2021 a las 1:50, Paul Koning () escribi=C3=B3: > > > > On Jul 6, 2021, at 6:00 PM, Joel Sherrill wrote: > > > > I think you might get some ideas from the old m6809 port of gcc > > > > http://vectrexc.malban.de/documentation/gcc-6809-documentation > > > > That was an 8 bit CPU with only 64k memory space if I remember everythi= ng > > correctly. > > pdp11 also has 64k of address space, and the current gcc still supports i= t. > > > I think given an add with carry, gcc can be taught to use 8 bit > operations > > in sequence on larger types. I recall seeing this on the h8 or avr. > > pdp11 also, for 32 or 64 bit integers given 16 bit arithmetic. You don't > actually need add with carry, but having one makes the code more compact. > I think gcc core will do that flavor if the target code doesn't teach it > the more efficient way (which is easy to do). > > paul > >