From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id C2EA03858D38 for ; Fri, 23 Sep 2022 18:04:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C2EA03858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1663956256; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=kFbw2jxSuT49EE0Mjzol0BYxiSQmSzaA5zySpb3FKhg=; b=EIF86tKOIGFhVBI9k4c/O73+Rxdfd9VgYPYLN1gOgsm+Y4r0iAzNQVELaqE42Nl6NO9Sk2 Aw9DB/GGGoq295OZcFsICtYnA8VocXnS/J1PYDaRSlIPdJWI8Z5+T0N160B6OSmCJm/Lm0 elW/uQWtEOVXEvCNG71W6fMo5V6ZVAY= Received: from mail-yb1-f197.google.com (mail-yb1-f197.google.com [209.85.219.197]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-498-tjV2x_eKP0OEeJob3Xzl0w-1; Fri, 23 Sep 2022 14:04:15 -0400 X-MC-Unique: tjV2x_eKP0OEeJob3Xzl0w-1 Received: by mail-yb1-f197.google.com with SMTP id k14-20020a25e80e000000b006aa1160dfe3so507037ybd.5 for ; Fri, 23 Sep 2022 11:04:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=kFbw2jxSuT49EE0Mjzol0BYxiSQmSzaA5zySpb3FKhg=; b=ZywRne531YShs7iv0GBcK3IFH+Q7U1W5CKgm2rqssCd/lFttW+gVOW5Tdb/VvRtzPX 4pc/JJmnUlp07/I/eTCubFbzBw3Z4kg0OE1nZ8sCRb2OgckArshE2uvUIqHG6P42WS18 gznyjoVDD3rbARLiDL6E88VFcbqtwvTv+IhS+Gj7UfuLw+YyUbe4Xmuw2g2WkjMK4qH6 CY7QjAjD2k3aRQzB7qAfpLT3KkCwdg3o9bdyDTtSUNyJR57aPmAFJIdYedj64SMIIX8l 3YlR8o9FHgcbnhx54M0YAZtmF4ZjwNP59U/8vvY6nSBrpMfOjeEKE+Oke2li7jhpmRuj oa+Q== X-Gm-Message-State: ACrzQf3n8fsma78f+MND7kkWqfcGg6yDDZu/Zr9boWiT+5TV0ysFDUnm 19pJI2A2Hiw8mrPwrra7tPVTiRJIkswy8DEjsTbSZ3tS5K1rBGPOSCe4gVo5M5lZ+EiucGkWN1x +tfrucJkxN6hZrqtwHhneKDTXg+MO07g= X-Received: by 2002:a5b:c4b:0:b0:6ae:ca4a:59e5 with SMTP id d11-20020a5b0c4b000000b006aeca4a59e5mr10326007ybr.246.1663956254149; Fri, 23 Sep 2022 11:04:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM66SRH9mtenKGyQbv5Ur7fgOKaQsmtndcryIMZeaYrVcpvvWLXxWdysilvQdepk4Bek61I16NoPqSt4Ximtyig= X-Received: by 2002:a5b:c4b:0:b0:6ae:ca4a:59e5 with SMTP id d11-20020a5b0c4b000000b006aeca4a59e5mr10325983ybr.246.1663956253857; Fri, 23 Sep 2022 11:04:13 -0700 (PDT) MIME-Version: 1.0 References: <20220923113713.103017-1-sebastian.huber@embedded-brains.de> In-Reply-To: <20220923113713.103017-1-sebastian.huber@embedded-brains.de> From: Jeff Johnston Date: Fri, 23 Sep 2022 14:04:02 -0400 Message-ID: Subject: Re: [PATCH] powerpc/setjmp: Add 64-bit support To: Sebastian Huber Cc: Newlib X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/alternative; boundary="0000000000006eee6705e95c01eb" X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000006eee6705e95c01eb Content-Type: text/plain; charset="UTF-8" Hi Sebastian, Just a couple of questions/issues: 1. How did you arrive at 70 doubles and 43 doubles length values? 2. It appears that __SPE__ is not accounted for in setjmp.h -- Jeff J. On Fri, Sep 23, 2022 at 7:37 AM Sebastian Huber < sebastian.huber@embedded-brains.de> wrote: > Use 64-bit store/load instructions to save/restore the general-purpose > registers. > --- > newlib/libc/include/machine/setjmp.h | 8 +++ > newlib/libc/machine/powerpc/setjmp.S | 79 ++++++++++++++++++++++++---- > 2 files changed, 78 insertions(+), 9 deletions(-) > > diff --git a/newlib/libc/include/machine/setjmp.h > b/newlib/libc/include/machine/setjmp.h > index 0bb53238b..53878a03d 100644 > --- a/newlib/libc/include/machine/setjmp.h > +++ b/newlib/libc/include/machine/setjmp.h > @@ -173,11 +173,19 @@ _BEGIN_STD_C > #endif > > #ifdef __PPC__ > +#ifdef __powerpc64__ > +#ifdef __ALTIVEC__ > +#define _JBLEN 70 > +#else > +#define _JBLEN 43 > +#endif > +#else > #ifdef __ALTIVEC__ > #define _JBLEN 64 > #else > #define _JBLEN 32 > #endif > +#endif > #define _JBTYPE double > #endif > > diff --git a/newlib/libc/machine/powerpc/setjmp.S > b/newlib/libc/machine/powerpc/setjmp.S > index f4ccd1bb5..f1f8ac28f 100644 > --- a/newlib/libc/machine/powerpc/setjmp.S > +++ b/newlib/libc/machine/powerpc/setjmp.S > @@ -1,6 +1,7 @@ > /* This is a simple version of setjmp and longjmp for the PowerPC. > Ian Lance Taylor, Cygnus Support, 9 Feb 1994. > - Modified by Jeff Johnston, Red Hat Inc. 2 Oct 2001. */ > + Modified by Jeff Johnston, Red Hat Inc. 2 Oct 2001. > + Modified by Sebastian Huber, embedded brains GmbH. 22 Sep 2022. */ > > #include "ppc-asm.h" > > @@ -40,6 +41,31 @@ FUNC_START(setjmp) > stored. Note that we are not adding 168 because the next > store instruction uses an offset of 4. */ > addi 3,3,164 > +#elif __powerpc64__ > + /* In the first store, add 16 to r3 so that the subsequent > floating > + point stores are aligned on an 8 byte boundary and the Altivec > + stores are aligned on a 16 byte boundary. */ > + stdu 1,16(3) # offset 16 > + stdu 2,8(3) # offset 24 > + stdu 13,8(3) # offset 32 > + stdu 14,8(3) # offset 40 > + stdu 15,8(3) # offset 48 > + stdu 16,8(3) # offset 56 > + stdu 17,8(3) # offset 64 > + stdu 18,8(3) # offset 72 > + stdu 19,8(3) # offset 80 > + stdu 20,8(3) # offset 88 > + stdu 21,8(3) # offset 96 > + stdu 22,8(3) # offset 104 > + stdu 23,8(3) # offset 112 > + stdu 24,8(3) # offset 120 > + stdu 25,8(3) # offset 128 > + stdu 26,8(3) # offset 136 > + stdu 27,8(3) # offset 144 > + stdu 28,8(3) # offset 152 > + stdu 29,8(3) # offset 160 > + stdu 30,8(3) # offset 168 > + stdu 31,8(3) # offset 176 > #else > stw 1,0(3) # offset 0 > stwu 2,4(3) # offset 4 > @@ -64,10 +90,15 @@ FUNC_START(setjmp) > stwu 31,4(3) # offset 80 > #endif > > - /* From this point on until the end of this function, add 84 > - to the offset shown if __SPE__. This difference comes from > - the fact that we save 21 64-bit registers instead of 21 > - 32-bit registers above. */ > + /* If __SPE__, then add 84 to the offset shown from this point on > until > + the end of this function. This difference comes from the fact > that > + we save 21 64-bit registers instead of 21 32-bit registers > above. > + > + If __powerpc64__, then add 96 to the offset shown from this > point on until > + the end of this function. This difference comes from the fact > that > + we save 21 64-bit registers instead of 21 32-bit registers > above and > + we take alignement requirements of floating point and Altivec > stores > + into account. */ > mflr 4 > stwu 4,4(3) # offset 84 > mfcr 4 > @@ -188,6 +219,31 @@ FUNC_START(longjmp) > loaded. Note that we are not adding 168 because the next > load instruction uses an offset of 4. */ > addi 3,3,164 > +#elif __powerpc64__ > + /* In the first load, add 16 to r3 so that the subsequent floating > + point loades are aligned on an 8 byte boundary and the Altivec > + loads are aligned on a 16 byte boundary. */ > + ldu 1,16(3) # offset 16 > + ldu 2,8(3) # offset 24 > + ldu 13,8(3) # offset 32 > + ldu 14,8(3) # offset 40 > + ldu 15,8(3) # offset 48 > + ldu 16,8(3) # offset 56 > + ldu 17,8(3) # offset 64 > + ldu 18,8(3) # offset 72 > + ldu 19,8(3) # offset 80 > + ldu 20,8(3) # offset 88 > + ldu 21,8(3) # offset 96 > + ldu 22,8(3) # offset 104 > + ldu 23,8(3) # offset 112 > + ldu 24,8(3) # offset 120 > + ldu 25,8(3) # offset 128 > + ldu 26,8(3) # offset 136 > + ldu 27,8(3) # offset 144 > + ldu 28,8(3) # offset 152 > + ldu 29,8(3) # offset 160 > + ldu 30,8(3) # offset 168 > + ldu 31,8(3) # offset 176 > #else > lwz 1,0(3) # offset 0 > lwzu 2,4(3) # offset 4 > @@ -211,10 +267,15 @@ FUNC_START(longjmp) > lwzu 30,4(3) # offset 76 > lwzu 31,4(3) # offset 80 > #endif > - /* From this point on until the end of this function, add 84 > - to the offset shown if __SPE__. This difference comes from > - the fact that we restore 21 64-bit registers instead of 21 > - 32-bit registers above. */ > + /* If __SPE__, then add 84 to the offset shown from this point on > until > + the end of this function. This difference comes from the fact > that > + we restore 21 64-bit registers instead of 21 32-bit registers > above. > + > + If __powerpc64__, then add 96 to the offset shown from this > point on until > + the end of this function. This difference comes from the fact > that > + we restore 21 64-bit registers instead of 21 32-bit registers > above and > + we take alignement requirements of floating point and Altivec > loads > + into account. */ > lwzu 5,4(3) # offset 84 > mtlr 5 > lwzu 5,4(3) # offset 88 > -- > 2.35.3 > > --0000000000006eee6705e95c01eb--