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Date: Wed, 30 Nov 2022 16:49:31 +0000 Message-ID: X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1EUR03FT015:EE_|AS8PR08MB8994:EE_ X-MS-Office365-Filtering-Correlation-Id: 7974fdb5-1669-4fa5-e72d-08dad2f2dbe6 NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ulfM/aBQUUpvGUP3ovJvIv//AtCzu+wsEqn6qTAMkfVmeELwLvtBVYdtEd5+Ho0nq2cqTliQP87G3k/AJ/9w7K05FwvOinkmotS9N+014FwSxUQ8eShEbczARP9jKa5Qy9ejmxGZ6u0vVYWRkNysda5kGkSof+dmj3hwXuZupNfFsa91KyI2A8qb43Ig25XFWep9vPrMu2D5mtT12ygdtILeoJgO3qRyD9DmjBstE16TSSr1BI9KzSW2K8C483pMKhWMitTMJNa3ViL+0Jt34KljOzq+558kmavpbWe2+ku+1CmN/9kBw1qC7ldIuxWn9AQ/gONWZozwFEJmysVWMQPsLbfr96nhLJSbwVb9OLgWhsZkdfD/eHC2bZtWE++NK2/mH+h1N++TIEOZSYhZM8HOCHmVWlZb7JjeL7pKzcen/cd3OyOOAy3Tto5gqMmWlBx6XrigaEvSzdwdQbJbYq1BvGg2DPu1z5Bw3jdssrOmOpeUN27wkAOb7ouAgRe8x0kR6IOquR1KFiLy7A6TRJ4Ka7ilpuEUL1j/ib+CFQWBLXKQhCyk9A0g4YVQqaq+WPm9vv6ypeoVDmdDmrS+RQrkTSdUtgckk9YSID/lz48pe2r5/R3NuUDKU7dkkCs20lQNcIhZJgF5qSUT26qiraczYSl4iC02Kmgk7aU/tz3b1V6pB58WsMadApsrgU5Wd+EZ4P0qZrVxhFAQNGL2eeSwqdFW4+GzMwLJ95SgydYwITFrC5N067J1sfGes45e X-Forefront-Antispam-Report: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(346002)(39860400002)(376002)(451199015)(46966006)(40470700004)(36840700001)(186003)(31686004)(36860700001)(2906002)(83380400001)(81166007)(70206006)(70586007)(356005)(8676002)(40460700003)(41300700001)(82310400005)(82740400003)(478600001)(26005)(40480700001)(47076005)(336012)(5660300002)(8936002)(235185007)(33964004)(4326008)(86362001)(4001150100001)(426003)(6916009)(54906003)(316002)(31696002)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2022 16:49:33.8826 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7974fdb5-1669-4fa5-e72d-08dad2f2dbe6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[40.67.248.234];Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT015.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8994 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --===============1517536779420346181== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Hi All, In _stack_init function of crt0.S file, when the current mode is not user mode, all the processor modes are parsed and the corresponding stack limit are set for these modes for all A-profile and R-profile CPU's. But when the current processor mode is hypervisor mode, changing to any other mode using CPSR will result in an illegal instruction as per Arm-arm and simulator throws undefined instruction exception. This patch prevent the change of hypervisor mode to any other mode in _stack_init function in crt0.S files. Regression tested on arm-none-eabi target for newlib and newlib-nano and found no regressions. Ok for newlib master? Regards, Srinath. libgloss/ChangeLog: 2022-11-28 Srinath Parvathaneni * arm/crt0.S (_stack_init): Add check for hypervisor mode. newlib/ChangeLog: 2022-11-28 Srinath Parvathaneni * libc/sys/arm/crt0.S (_stack_init): Add check for hypervisor mode. ############### Attachment also inlined for ease of reply ############### diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index 78515180bf06f1da37669e4c7e6608c76e1b096d..e3c0ca00fd5d25e8059be07a0fb62490350b4dcb 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -148,13 +148,17 @@ /* M profile doesn't have CPSR register. */ #if (__ARM_ARCH_PROFILE != 'M') /* Following code is compatible for both ARM and Thumb ISA. */ - mrs r4, CPSR - /* Test mode bits - in User of all are 0. */ - tst r4, #(CPSR_M_MASK) + mrs r4, CPSR + mov r3, sp /* Save input SP value. */ + /* Test mode bits - in User mode all are 0. */ + ands r1, r4, #(CPSR_M_MASK) /* "eq" means r4 AND #0x0F is 0. */ beq .Lskip_cpu_modes - mov r3, sp /* Save input SP value. */ + /* Test mode bits - in Hypervisor Mode value is 0X0A. */ + cmp r1, #(CPSR_M_HYP) + /* "eq" means hypervisor mode and change of mode is not acceptable. */ + beq .Lskip_cpu_hyp_mode /* FIQ mode, interrupts disabled. */ mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK) @@ -236,6 +240,7 @@ sub sl, r3, #64 << 10 #endif #endif +.Lskip_cpu_hyp_mode: FN_RETURN FN_EH_END diff --git a/newlib/libc/sys/arm/crt0.S b/newlib/libc/sys/arm/crt0.S index 6b01d8a88b77f44b1ba495aa1f69156f12749527..b974c36c92c8f092643f63d2056927a107a1e85b 100644 --- a/newlib/libc/sys/arm/crt0.S +++ b/newlib/libc/sys/arm/crt0.S @@ -148,13 +148,17 @@ /* M profile doesn't have CPSR register. */ #if (__ARM_ARCH_PROFILE != 'M') /* Following code is compatible for both ARM and Thumb ISA. */ - mrs r4, CPSR - /* Test mode bits - in User of all are 0. */ - tst r4, #(CPSR_M_MASK) + mrs r4, CPSR + mov r3, sp /* Save input SP value. */ + /* Test mode bits - in User mode all are 0. */ + ands r1, r4, #(CPSR_M_MASK) /* "eq" means r4 AND #0x0F is 0. */ - beq .Lskip_cpu_modes + beq .Lskip_cpu_modes - mov r3, sp /* Save input SP value. */ + /* Test mode bits - in Hypervisor Mode value is 0X0A. */ + cmp r1, #(CPSR_M_HYP) + /* "eq" means hypervisor mode and change of mode is not acceptable. */ + beq .Lskip_cpu_hyp_mode /* FIQ mode, interrupts disabled. */ mov r1, #(CPSR_M_FIQ|CPSR_M_32BIT|CPSR_I_MASK|CPSR_F_MASK) @@ -236,6 +240,7 @@ sub sl, r3, #64 << 10 #endif #endif +.Lskip_cpu_hyp_mode: FN_RETURN FN_EH_END --===============1517536779420346181== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="rb16656.patch" ZGlmZiAtLWdpdCBhL2xpYmdsb3NzL2FybS9jcnQwLlMgYi9saWJnbG9zcy9hcm0vY3J0MC5TCmlu ZGV4IDc4NTE1MTgwYmYwNmYxZGEzNzY2OWU0YzdlNjYwOGM3NmUxYjA5NmQuLmUzYzBjYTAwZmQ1 ZDI1ZTgwNTliZTA3YTBmYjYyNDkwMzUwYjRkY2IgMTAwNjQ0Ci0tLSBhL2xpYmdsb3NzL2FybS9j cnQwLlMKKysrIGIvbGliZ2xvc3MvYXJtL2NydDAuUwpAQCAtMTQ4LDEzICsxNDgsMTcgQEAKIAkv KiBNIHByb2ZpbGUgZG9lc24ndCBoYXZlIENQU1IgcmVnaXN0ZXIuICAqLwogI2lmIChfX0FSTV9B UkNIX1BST0ZJTEUgIT0gJ00nKQogCS8qIEZvbGxvd2luZyBjb2RlIGlzIGNvbXBhdGlibGUgZm9y IGJvdGggQVJNIGFuZCBUaHVtYiBJU0EuICAqLwotCW1ycwlyNCwgQ1BTUgotCS8qIFRlc3QgbW9k ZSBiaXRzIC0gaW4gVXNlciBvZiBhbGwgYXJlIDAuICAqLwotCXRzdAlyNCwgIyhDUFNSX01fTUFT SykKKwltcnMgICAgIHI0LCBDUFNSCisJbW92CXIzLCBzcCAvKiBTYXZlIGlucHV0IFNQIHZhbHVl LiAgKi8KKwkvKiBUZXN0IG1vZGUgYml0cyAtIGluIFVzZXIgbW9kZSBhbGwgYXJlIDAuICAqLwor CWFuZHMJcjEsIHI0LCAjKENQU1JfTV9NQVNLKQogCS8qICJlcSIgbWVhbnMgcjQgQU5EICMweDBG IGlzIDAuICAqLwogCWJlcQkuTHNraXBfY3B1X21vZGVzCiAKLQltb3YJcjMsIHNwIC8qIFNhdmUg aW5wdXQgU1AgdmFsdWUuICAqLworCS8qIFRlc3QgbW9kZSBiaXRzIC0gaW4gSHlwZXJ2aXNvciBN b2RlIHZhbHVlIGlzIDBYMEEuICAqLworCWNtcAlyMSwgIyhDUFNSX01fSFlQKQorCS8qICJlcSIg bWVhbnMgaHlwZXJ2aXNvciBtb2RlIGFuZCBjaGFuZ2Ugb2YgbW9kZSBpcyBub3QgYWNjZXB0YWJs ZS4gICovCisJYmVxCS5Mc2tpcF9jcHVfaHlwX21vZGUKIAogCS8qIEZJUSBtb2RlLCBpbnRlcnJ1 cHRzIGRpc2FibGVkLiAgKi8KIAltb3YJcjEsICMoQ1BTUl9NX0ZJUXxDUFNSX01fMzJCSVR8Q1BT Ul9JX01BU0t8Q1BTUl9GX01BU0spCkBAIC0yMzYsNiArMjQwLDcgQEAKIAlzdWIJc2wsIHIzLCAj NjQgPDwgMTAKIAkjZW5kaWYKICNlbmRpZgorLkxza2lwX2NwdV9oeXBfbW9kZToKIAogCUZOX1JF VFVSTgogCUZOX0VIX0VORApkaWZmIC0tZ2l0IGEvbmV3bGliL2xpYmMvc3lzL2FybS9jcnQwLlMg Yi9uZXdsaWIvbGliYy9zeXMvYXJtL2NydDAuUwppbmRleCA2YjAxZDhhODhiNzdmNDRiMWJhNDk1 YWExZjY5MTU2ZjEyNzQ5NTI3Li5iOTc0YzM2YzkyYzhmMDkyNjQzZjYzZDIwNTY5MjdhMTA3YTFl ODViIDEwMDY0NAotLS0gYS9uZXdsaWIvbGliYy9zeXMvYXJtL2NydDAuUworKysgYi9uZXdsaWIv bGliYy9zeXMvYXJtL2NydDAuUwpAQCAtMTQ4LDEzICsxNDgsMTcgQEAKIAkvKiBNIHByb2ZpbGUg ZG9lc24ndCBoYXZlIENQU1IgcmVnaXN0ZXIuICAqLwogI2lmIChfX0FSTV9BUkNIX1BST0ZJTEUg IT0gJ00nKQogCS8qIEZvbGxvd2luZyBjb2RlIGlzIGNvbXBhdGlibGUgZm9yIGJvdGggQVJNIGFu ZCBUaHVtYiBJU0EuICAqLwotCW1ycwlyNCwgQ1BTUgotCS8qIFRlc3QgbW9kZSBiaXRzIC0gaW4g VXNlciBvZiBhbGwgYXJlIDAuICAqLwotCXRzdAlyNCwgIyhDUFNSX01fTUFTSykKKwltcnMgICAg IHI0LCBDUFNSCisJbW92ICAgICByMywgc3AgLyogU2F2ZSBpbnB1dCBTUCB2YWx1ZS4gICovCisJ LyogVGVzdCBtb2RlIGJpdHMgLSBpbiBVc2VyIG1vZGUgYWxsIGFyZSAwLiAgKi8KKwlhbmRzICAg IHIxLCByNCwgIyhDUFNSX01fTUFTSykKIAkvKiAiZXEiIG1lYW5zIHI0IEFORCAjMHgwRiBpcyAw LiAgKi8KLQliZXEJLkxza2lwX2NwdV9tb2RlcworCWJlcSAgICAgLkxza2lwX2NwdV9tb2Rlcwog Ci0JbW92CXIzLCBzcCAvKiBTYXZlIGlucHV0IFNQIHZhbHVlLiAgKi8KKwkvKiBUZXN0IG1vZGUg Yml0cyAtIGluIEh5cGVydmlzb3IgTW9kZSB2YWx1ZSBpcyAwWDBBLiAgKi8KKwljbXAgICAgIHIx LCAjKENQU1JfTV9IWVApCisJLyogImVxIiBtZWFucyBoeXBlcnZpc29yIG1vZGUgYW5kIGNoYW5n ZSBvZiBtb2RlIGlzIG5vdCBhY2NlcHRhYmxlLiAgKi8KKwliZXEgICAgIC5Mc2tpcF9jcHVfaHlw X21vZGUKIAogCS8qIEZJUSBtb2RlLCBpbnRlcnJ1cHRzIGRpc2FibGVkLiAgKi8KIAltb3YJcjEs ICMoQ1BTUl9NX0ZJUXxDUFNSX01fMzJCSVR8Q1BTUl9JX01BU0t8Q1BTUl9GX01BU0spCkBAIC0y MzYsNiArMjQwLDcgQEAKIAlzdWIJc2wsIHIzLCAjNjQgPDwgMTAKIAkjZW5kaWYKICNlbmRpZgor Lkxza2lwX2NwdV9oeXBfbW9kZToKIAogCUZOX1JFVFVSTgogCUZOX0VIX0VORAoKCgo= --===============1517536779420346181==--