From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 32867385840E for ; Tue, 22 Nov 2022 16:03:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 32867385840E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6881A1FB; Tue, 22 Nov 2022 08:03:15 -0800 (PST) Received: from [10.2.78.76] (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5DAB43F73D; Tue, 22 Nov 2022 08:03:08 -0800 (PST) Message-ID: Date: Tue, 22 Nov 2022 16:03:07 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 5/8] newlib: libc: memcpy M-profile PACBTI-enablement Content-Language: en-GB To: "Victor L. Do Nascimento" , newlib@sourceware.org Cc: Richard.Earnshaw@arm.com References: From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3495.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 26/10/2022 12:50, Victor L. Do Nascimento wrote: > Add function prologue/epilogue to conditionally add BTI landing pads > and/or PAC code generation & authentication instructions depending on > compilation flags. > --- > newlib/libc/machine/arm/memcpy-armv7m.S | 37 +++++++++++++++++-------- > 1 file changed, 26 insertions(+), 11 deletions(-) > > diff --git a/newlib/libc/machine/arm/memcpy-armv7m.S b/newlib/libc/machine/arm/memcpy-armv7m.S > index c8bff36f6..a74bacc97 100644 > --- a/newlib/libc/machine/arm/memcpy-armv7m.S > +++ b/newlib/libc/machine/arm/memcpy-armv7m.S > @@ -46,6 +46,8 @@ > __OPT_BIG_BLOCK_SIZE: Size of big block in words. Default to 64. > __OPT_MID_BLOCK_SIZE: Size of big block in words. Default to 16. > */ > +#include "arm_asm.h" > + > #ifndef __OPT_BIG_BLOCK_SIZE > #define __OPT_BIG_BLOCK_SIZE (4 * 16) > #endif > @@ -85,6 +87,8 @@ > .global memcpy > .thumb > .thumb_func > + .fnstart > + .cfi_startproc > .type memcpy, %function > memcpy: > @ r0: dst > @@ -93,10 +97,11 @@ memcpy: > #ifdef __ARM_FEATURE_UNALIGNED > /* In case of UNALIGNED access supported, ip is not used in > function body. */ > + prologue push_ip=HAVE_PAC_LEAF > mov ip, r0 > #else > - push {r0} > -#endif > + prologue 0 push_ip=HAVE_PAC_LEAF > +#endif /* __ARM_FEATURE_UNALIGNED */ > orr r3, r1, r0 > ands r3, r3, #3 > bne .Lmisaligned_copy > @@ -135,13 +140,13 @@ memcpy: > ldr r3, [r1], #4 > str r3, [r0], #4 > END_UNROLL > -#else /* __ARM_ARCH_7M__ */ > +#else Why this change? > ldr r3, [r1, \offset] > str r3, [r0, \offset] > END_UNROLL > adds r0, __OPT_MID_BLOCK_SIZE > adds r1, __OPT_MID_BLOCK_SIZE > -#endif > +#endif /* __ARM_ARCH_7M__ */ And this? Please put them back as they were. [Just for the record, this test is using a deprecated GCC extension and needs rewriting using the appropriate feature tests from ACLE; but that's not something you need to fix.] Otherwise OK. R. > subs r2, __OPT_MID_BLOCK_SIZE > bhs .Lmid_block_loop > > @@ -178,15 +183,17 @@ memcpy: > #endif /* __ARM_FEATURE_UNALIGNED */ > > .Ldone: > + .cfi_remember_state > #ifdef __ARM_FEATURE_UNALIGNED > mov r0, ip > + epilogue push_ip=HAVE_PAC_LEAF > #else > - pop {r0} > -#endif > - bx lr > + epilogue 0 push_ip=HAVE_PAC_LEAF > +#endif /* __ARM_FEATURE_UNALIGNED */ > > .align 2 > .Lmisaligned_copy: > + .cfi_restore_state > #ifdef __ARM_FEATURE_UNALIGNED > /* Define label DST_ALIGNED to BIG_BLOCK. It will go to aligned copy > once destination is adjusted to aligned. */ > @@ -247,6 +254,9 @@ memcpy: > /* dst is aligned, but src isn't. Misaligned copy. */ > > push {r4, r5} > + .cfi_adjust_cfa_offset 8 > + .cfi_rel_offset 4, 0 > + .cfi_rel_offset 5, 4 > subs r2, #4 > > /* Backward r1 by misaligned bytes, to make r1 aligned. > @@ -299,6 +309,9 @@ memcpy: > adds r2, #4 > subs r1, ip > pop {r4, r5} > + .cfi_restore 4 > + .cfi_restore 5 > + .cfi_adjust_cfa_offset -8 > > #endif /* __ARM_FEATURE_UNALIGNED */ > > @@ -321,9 +334,11 @@ memcpy: > > #ifdef __ARM_FEATURE_UNALIGNED > mov r0, ip > + epilogue push_ip=HAVE_PAC_LEAF > #else > - pop {r0} > -#endif > - bx lr > - > + epilogue 0 push_ip=HAVE_PAC_LEAF > +#endif /* __ARM_FEATURE_UNALIGNED */ > + .cfi_endproc > + .cantunwind > + .fnend > .size memcpy, .-memcpy