From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=b7rM=63=foss.arm.com=Richard.Earnshaw@sourceware.org>
Received: from foss.arm.com (foss.arm.com [217.140.110.172])
	by sourceware.org (Postfix) with ESMTP id B1E013858CDB
	for <newlib@sourceware.org>; Fri,  3 Mar 2023 13:35:06 +0000 (GMT)
DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B1E013858CDB
Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com
Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com
Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])
	by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B465B143D;
	Fri,  3 Mar 2023 05:35:49 -0800 (PST)
Received: from [10.2.78.76] (unknown [10.2.78.76])
	by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DBC553F93E;
	Fri,  3 Mar 2023 05:35:05 -0800 (PST)
Message-ID: <ea66814c-40f5-e545-73aa-3adfcd21a426@foss.arm.com>
Date: Fri, 3 Mar 2023 13:35:04 +0000
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.7.1
Subject: Re: [PATCH v3][Newlib] arm: Restrict processor mode change when in
 hypervisor mode.
Content-Language: en-GB
To: Srinath Parvathaneni <srinath.parvathaneni@arm.com>, newlib@sourceware.org
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>
References: <82d6ffe6-8198-f2d6-8f8f-eb86172db5a5@arm.com>
From: Richard Earnshaw <Richard.Earnshaw@foss.arm.com>
In-Reply-To: <82d6ffe6-8198-f2d6-8f8f-eb86172db5a5@arm.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit
X-Spam-Status: No, score=-3488.0 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org
List-Id: <newlib.sourceware.org>

Pushed (with tweaks to the commit message).

R.

On 03/03/2023 13:12, Srinath Parvathaneni wrote:
> Hi All,
> 
> In _stack_init function of crt0.S file, when the current mode is not 
> user mode,
> all the processor modes are parsed and the corresponding stack limit are 
> set for
> these modes for all A-profile and R-profile CPU's. But if a CPU 
> implements EL2
> as its highest exception level, then the core (or a model of it) will 
> start in that
> mode. For example, with Cortex-R52 the processor starts by default is 
> hypervisor
> mode (EL2), changing to any other mode using CPSR will result in an illegal
> instruction as per Arm-arm.
> This patch prevent the change of Hypervisor mode to any other EL1 modes in
> _stack_init function in crt0.S files and does not set the stack limit 
> for those
> EL1 modes.
> 
> Regression tested on arm-none-eabi target for newlib and newlib-nano and 
> found
> no regressions.
> 
> Ok for newlib master?
> 
> Regards,
> Srinath.
> 
> libgloss/ChangeLog:
> 
> 2023-03-03  Srinath Parvathaneni<srinath.parvathaneni@arm.com>
> 
>          * arm/crt0.S (_stack_init): Add check for hypervisor mode.
> 
> newlib/ChangeLog:
> 
> 2023-03-03  Srinath Parvathaneni<srinath.parvathaneni@arm.com>
> 
>          * libc/sys/arm/crt0.S (_stack_init): Add check for hypervisor 
> mode.