From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from bird.elm.relay.mailchannels.net (bird.elm.relay.mailchannels.net [23.83.212.17]) by sourceware.org (Postfix) with ESMTPS id 721FA3858D39 for ; Mon, 6 Mar 2023 13:24:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 721FA3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nadler.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nadler.com X-Sender-Id: dreamhost|x-authsender|drn@nadler.com Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id AF5875C235B; Mon, 6 Mar 2023 13:24:34 +0000 (UTC) Received: from pdx1-sub0-mail-a309.dreamhost.com (unknown [127.0.0.6]) (Authenticated sender: dreamhost) by relay.mailchannels.net (Postfix) with ESMTPA id 222275C2350; Mon, 6 Mar 2023 13:24:34 +0000 (UTC) ARC-Seal: i=1; s=arc-2022; d=mailchannels.net; t=1678109074; a=rsa-sha256; cv=none; b=GnRUoYKPnIBhQzpk6wH8EN4A3PqBdt5Q26GrERAS9XzmeoXUC6UO0np3moQV5JbUCgmXxo z7k2A+0eIe/GY9WR3v2w5KmUftitIIqAu9lF5c72KhJXkF0qpx0p24uqTwVGQ75+6e/DXg FGXa8+z0//VFlP6pmEoDX53guVWQBI5ejkCJhywQ48cb6LwfbF0ozOxgfcwF/+0WVlstr6 Zu/JhFVOQ2HdZ8oRRO/XIpawrQm7Lr2k0GvR6nOW7f/0wYygX5wwIWFxT5xs2Yn9G28GMv sNOKM7TSqio8fXyeJeHiJqXDIKFPK6yWUjXkEvYOPdu+xJlL/Y5qb1XH4AlOlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=mailchannels.net; s=arc-2022; t=1678109074; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references:dkim-signature; bh=kkcP4k1Ytz/q8lFOy3CZdI351D7x4f4eKdKrkgqdOb0=; b=5jPYRI7GEMfLTbyjPZVJA3/v76BpC7Kl9mA5ZKcS/zSXIC7iroC/b0WQUj847jF5tEgMgy KxZbSDO3NCai2f49Fe4XVLowfHFwUSQhSSgBv01YKX0mpo/eShDY3czgApxY4mdly46kZ0 1uW/OLGSKrsY8AqEhvtSR/pZUS5PPV5yezfDcfAsiVGAef/kBOaUSfiJ43DoOx6jApgoZ7 oOOQll6HjFkBacO0eun44hmQmHxDrEEkcNuk3Wf4CsJ7mOwXuJGol5AUM3y1OxfXMLglk5 RBBcjhOhE0dxFW1AX19Lh1hfbcNjG9ErFpdDd+1UGuk8Xrz8ITenOI9ps7xECA== ARC-Authentication-Results: i=1; rspamd-69778c65cd-tj2zs; auth=pass smtp.auth=dreamhost smtp.mailfrom=drn@nadler.com X-Sender-Id: dreamhost|x-authsender|drn@nadler.com X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|drn@nadler.com X-MailChannels-Auth-Id: dreamhost X-Company-Troubled: 30c983e92eae7cd7_1678109074581_1993434842 X-MC-Loop-Signature: 1678109074581:3980993221 X-MC-Ingress-Time: 1678109074581 Received: from pdx1-sub0-mail-a309.dreamhost.com (pop.dreamhost.com [64.90.62.162]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384) by 100.126.40.207 (trex/6.7.2); Mon, 06 Mar 2023 13:24:34 +0000 Received: from [172.16.26.228] (075-112-168-179.res.spectrum.com [75.112.168.179]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) (Authenticated sender: drn@nadler.com) by pdx1-sub0-mail-a309.dreamhost.com (Postfix) with ESMTPSA id 4PVfSK3Qg3z6F; Mon, 6 Mar 2023 05:24:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nadler.com; s=dreamhost; t=1678109073; bh=1chJz13dQCuPqs+MopOtNfvgXZ6Awo47+7+B2H7wZq8=; h=Content-Type:Date:Subject:To:From; b=pmKwtW6dPT1BRDcSozwu3UiI8KS90c/xNN+NG0OmuXCp8rbcFaBlwGWDhmKRyw1Ic m8pA/uDPM0PmGB6YSEceP3afot39ZegLE8QP1zuZqS8vCXVg4CO8z7LnvL6N0nSRy/ aJz+p3diyCDeXEUmlUzds9daWukwKe1lPo+jqCGCGIGIEI2hbjTVtotMc2y0wOaSDP +1d/dqpzMJEX04JIBuThEk8hhkjIyfK8r8PDrnRh1cbwLfyu1ZZrE1OT63RyYqkSZq pLgjcswgak9LEtZYpyamdcwy1i6H3ADu/Mz9YGFovofPXrt5QDQ7XMHkduyDNhM5iJ 5ny2IJ5lvTmng== Content-Type: multipart/alternative; boundary="------------wxIQ2nSWEM3I0eMMnNqzy0C2" Message-ID: Date: Mon, 6 Mar 2023 08:24:33 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: Problem with SBRK not returning from call on bare metal risk Content-Language: en-US To: Damien Towning , newlib@sourceware.org References: From: Dave Nadler In-Reply-To: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HTML_MESSAGE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------wxIQ2nSWEM3I0eMMnNqzy0C2 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Damien - You need to verify the sbrk you're using actually provides the correct addresses. In cases I'm familiar with, sbrk is provided by the chip-specific toolchain and not newlib. Providing your own sbrk is not all bad... Also, you need to be sure how newlib was built in the toolchain you are using; you didn't show us the newlib configuration? This might provide some help: https://nadler.com/embedded/newlibAndFreeRTOS.html Hope this helps! Best Regards, Dave On 3/6/2023 2:36 AM, Damien Towning wrote: > So a bit of a background. I have the bonfire Risc-V 32 core running on a > T-35 FPGA board. The metal part of this is working great. The processor > runs. I've got it to turn around the segment display on the board. I've > also implemented my own _sbrk and got that to work I think consistently > with malloc. Now in my Risc-v 32 toolchain I have the newlib and I have > brought that in and with my own wrapped _sbrk I am able to use the system > defined malloc. But I am not entirely happy with this because I don't want > to be wrapping every function I encounter. So for example today I found > myself wrapping srand and rand. So I am pretty sure the reason my > nano_newlib isn't working is something to do with either not having the > correct variable names in my firmware.ld or something to do with disabling > the re-entrant behaviour of newlib. I've included in this email my > firmware.ld,platform.h,c code example. What happens is I call the _sbrk(0) > and ( in the simulator I am also running this in ) I never see a bad opcode > generated. It just seems like the processor goes away and never comes back. > Does anybody have any suggestions as to what might cause this sort of > problem ? I'd like to use the sbrk and other funcitons within the newlib > itself if possible without rolling my own. > > ------------- firmware.ld > MEMORY > { > > RAM (rwx) : ORIGIN = 0x0C000000, LENGTH = 512K > } > > ENTRY(_start) > > SECTIONS > { > _rombase = 0x0C000000; > > . = 0x0; > > .text : { > *(.init) > *(.text.*) > > } > RAM > > .data ALIGN(4) : { > *(.rodata.*) > *(.rodata) > *(.eh_frame) > *(.sdata) > *(.data) > *(.sbss) > *(.sbss.*) > *(.gnu.linkonce.sb.*) > *(.bss) > *(.bss.*) > *(.gnu.linkonce.b.*) > *(COMMON) > > end = .; _end = .; __end = .; > > } > RAM > > _heap_end = _end; > _heap_prev_end = _end; > > } > > PROVIDE(__heap_end = _end); > PROVIDE(__prev_heap_end = _end); > PROVIDE(__heap_start = _end+128K); > > PROVIDE(__stack_top = ORIGIN(RAM) + LENGTH(RAM)); > PROVIDE(__stack_start = ORIGIN(RAM) + LENGTH(RAM)); > > PROVIDE(__heap_size = 128K ); > PROVIDE(__stack_size = 128K ); > > > > /* > 0x0C000000 +-------------------+ > | | > | ROM / Flash | > 0x0C080000 +-------------------+ > | | > | .data | > |-------------------| > | .bss / .sbss | > |-------------------| > | _end | > |-------------------| > | Heap | > |-------------------| > | Stack | > 0xXXXXXXXX +-------------------+ > */ > -------------------------------------------------------------------------------------- > > ---------platform.h > ---------------------------------------------------------------- > #ifndef BASIC_PLATFORM_H > #define BASIC_PLATFORM_H > > // New Defintions for new bonfire-soc-io core > #define IO_BASE 0x04000000 > #define SOC_IO_OFFSET 0x10000 // Offset from one I/O Device to the next > (64K range) > > #define UART0_BASE IO_BASE > #define SPIFLASH_BASE (IO_BASE+SOC_IO_OFFSET) > #define GPIO_BASE (IO_BASE+3*SOC_IO_OFFSET) > #define UART1_BASE (IO_BASE+2*SOC_IO_OFFSET) > > #define UART_BASE UART0_BASE // Backwards compatiblity > > #define MTIME_BASE 0x0FFFF0000 > > #define DRAM_BASE 0x0 > #define DRAM_SIZE 0 > #define DRAM_TOP (DRAM_BASE+DRAM_SIZE-1) > #define SRAM_BASE 0x0C000000 > #define SRAM_SIZE 524288 > #define SRAM_TOP (SRAM_BASE+SRAM_SIZE-1) > > //#define SYSCLK 12000000 > //#define SYSCLK 33333333 > //#define SYSCLK 24997500 > //#define SYSCLK 88786000 > #define EXT_SYSCLK 89015000 > > #define SYSCLK 24997500 > > //#define EXT_SYSCLK 92370000 /* For reasons not clear to me when any > change is made to the interface */ > /* configuration in Efinity and a new synthesis is done a clock time will > */ > /* be calculated so you must build your efinity project. Take that new > */ > /* time value. Update it here. Rebuild your hex file. Then rebuild your > */ > /* efinity project AGAIN > */ > > > #define TIME_UNIT 1e+9; // A billion > > #ifndef SIMULATOR > #define SCALAR 1 // Relative Scalar division for efinity build > #define BAUD_SCALAR 1 // Relative Scalar division for efinity build > #else > #define SCALAR 10000 // Relative Scalar division for simulator. Use for > any of your own timing since > #define BAUD_SCALAR 20 // simulator runs slower than real hardware > #endif > > #define CLK_PERIOD (TIME_UNIT / EXT_SYSCLK) // in ns... > > //#define DCACHE_SIZE 0 // (2048*4) // DCache Size in Bytes > > // Parameters for SPI Flash > > #define FLASHSIZE (8192*1024) > #define MAX_FLASH_IMAGESIZE (2024*1024) // Max 2MB of flash used for boot > image > #define FLASH_IMAGEBASE (1024*3072) // Boot Image starts at 3MB in Flash > > #define PLATFORM_BAUDRATE (115200*BAUD_SCALAR) > > #define NO_RECURSION > #define NO_SYSCALL > #define NO_FLASH > #define NO_XMODEM > #define NO_DRAMTEST > > //#define GPIO_TEST > > #endif > --------------------------------------------------------------------------------------------- > > ---- sim_hello.c > ------------------------------------------------------------------------ > // ============================================== > // T35 S100 Module Test Code > // Damien Towning - 2022 > // ============================================== > #include running on a T-35 FPGA board. The metal part of this is working great. The > processor runs. I've got it to turn around the segment display on the > board. I've also implemented my own _sbrk and got that to work I think > consistently with malloc. Now in my Risc-v 32 toolchain I have the newlib > and I have brought that in and with my own wrapped _sbrk I am able to use > the system defined malloc. But I am not entirely happy with this because I > don't want to be wrapping every function I encounter. So for example today > I found myself wrapping srand and rand. So I am pretty sure the reason my > nano_newlib isn't working is something to do with either not having the > correct variable names in my firmware.ld or something to do with disabling > the re-entrant behaviour of newlib. I've included in this email my > firmware.ld,platform.h,c code example. What happens is I call the _sbrk(0) > and ( in the simulator I am also running this in ) I never see a bad opcode > generated. It just seems like the processor goes away and never comes back. > Does anybody have any suggestions as to what might cause this sort of > problem ? I'd like to use the sbrk and other funcitons within the newlib > itself if possible without rolling my own. > > ------------- firmware.ld > MEMORY > { > > RAM (rwx) : ORIGIN = 0x0C000000, LENGTH = 512K > } > > ENTRY(_start) > > SECTIONS > { > _rombase = 0x0C000000; > > . = 0x0; > > .text : { > *(.init) > *(.text.*) > > } > RAM > > .data ALIGN(4) : { > *(.rodata.*) > *(.rodata) > *(.eh_frame) > *(.sdata) > *(.data) > *(.sbss) > *(.sbss.*) > *(.gnu.linkonce.sb.*) > *(.bss) > *(.bss.*) > *(.gnu.linkonce.b.*) > *(COMMON) > > end = .; _end = .; __end = .; > > } > RAM > > _heap_end = _end; > _heap_prev_end = _end; > > } > > PROVIDE(__heap_end = _end); > PROVIDE(__prev_heap_end = _end); > PROVIDE(__heap_start = _end+128K); > > PROVIDE(__stack_top = ORIGIN(RAM) + LENGTH(RAM)); > PROVIDE(__stack_start = ORIGIN(RAM) + LENGTH(RAM)); > > PROVIDE(__heap_size = 128K ); > PROVIDE(__stack_size = 128K ); > > > > /* > 0x0C000000 +-------------------+ > | | > | ROM / Flash | > 0x0C080000 +-------------------+ > | | > | .data | > |-------------------| > | .bss / .sbss | > |-------------------| > | _end | > |-------------------| > | Heap | > |-------------------| > | Stack | > 0xXXXXXXXX +-------------------+ > */ > -------------------------------------------------------------------------------------- > > ---------platform.h > ---------------------------------------------------------------- > #ifndef BASIC_PLATFORM_H > #define BASIC_PLATFORM_H > > // New Defintions for new bonfire-soc-io core > #define IO_BASE 0x04000000 > #define SOC_IO_OFFSET 0x10000 // Offset from one I/O Device to the next > (64K range) > > #define UART0_BASE IO_BASE > #define SPIFLASH_BASE (IO_BASE+SOC_IO_OFFSET) > #define GPIO_BASE (IO_BASE+3*SOC_IO_OFFSET) > #define UART1_BASE (IO_BASE+2*SOC_IO_OFFSET) > > #define UART_BASE UART0_BASE // Backwards compatiblity > > #define MTIME_BASE 0x0FFFF0000 > > #define DRAM_BASE 0x0 > #define DRAM_SIZE 0 > #define DRAM_TOP (DRAM_BASE+DRAM_SIZE-1) > #define SRAM_BASE 0x0C000000 > #define SRAM_SIZE 524288 > #define SRAM_TOP (SRAM_BASE+SRAM_SIZE-1) > > //#define SYSCLK 12000000 > //#define SYSCLK 33333333 > //#define SYSCLK 24997500 > //#define SYSCLK 88786000 > #define EXT_SYSCLK 89015000 > > #define SYSCLK 24997500 > > //#define EXT_SYSCLK 92370000 /* For reasons not clear to me when any > change is made to the interface */ > /* configuration in Efinity and a new synthesis is done a clock time will > */ > /* be calculated so you must build your efinity project. Take that new > */ > /* time value. Update it here. Rebuild your hex file. Then rebuild your > */ > /* efinity project AGAIN > */ > > > #define TIME_UNIT 1e+9; // A billion > > #ifndef SIMULATOR > #define SCALAR 1 // Relative Scalar division for efinity build > #define BAUD_SCALAR 1 // Relative Scalar division for efinity build > #else > #define SCALAR 10000 // Relative Scalar division for simulator. Use for > any of your own timing since > #define BAUD_SCALAR 20 // simulator runs slower than real hardware > #endif > > #define CLK_PERIOD (TIME_UNIT / EXT_SYSCLK) // in ns... > > //#define DCACHE_SIZE 0 // (2048*4) // DCache Size in Bytes > > // Parameters for SPI Flash > > #define FLASHSIZE (8192*1024) > #define MAX_FLASH_IMAGESIZE (2024*1024) // Max 2MB of flash used for boot > image > #define FLASH_IMAGEBASE (1024*3072) // Boot Image starts at 3MB in Flash > > #define PLATFORM_BAUDRATE (115200*BAUD_SCALAR) > > #define NO_RECURSION > #define NO_SYSCALL > #define NO_FLASH > #define NO_XMODEM > #define NO_DRAMTEST > > //#define GPIO_TEST > > #endif > --------------------------------------------------------------------------------------------- > > ---- sim_hello.c > ------------------------------------------------------------------------ > // ============================================== > // T35 S100 Module Test Code > // Damien Towning - 2022 > // ============================================== > #include > #include > > //#include > //#include > #include > #include > #include > #include "bonfire.h" > #include "uart.h" > #include "bonfire_gpio.h" > #include "mem_rw.h" > #include "console.h" > > extern void* sbrk(incr); > > > // ======================================== > // Main function > // ======================================== > int main() { > > setBaudRate(PLATFORM_BAUDRATE); > > caddr_t *ptr = sbrk(0); > // code never returns from sbrk > if (ptr == (void *)-1) { > printk("Failed to allocate memory\r\n"); > } > else { > printk("Allocated memory at : %p\r\n", (void *) &ptr); > } > return 0; > } > ------------------------------------------------------------------------------------ > --- Makefile > -------------------------------------------------------------------- > > .PHONY: all clean > > ARCH ?= rv32ia > ABI=ilp32 > PLATFORM ?= S100_T35 > > #TARGET_PREFIX ?= riscv32-unknown-linux-gnu > TARGET_PREFIX ?= riscv32-unknown-elf > TARGET_CC := $(TARGET_PREFIX)-gcc > TARGET_LD := $(TARGET_PREFIX)-gcc > TARGET_SIZE := $(TARGET_PREFIX)-size > TARGET_OBJCOPY := $(TARGET_PREFIX)-objcopy > HEXDUMP ?= hexdump > DATA2MEM = /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/data2mem > > #PROJROOT = ../../.. > #TOPLEVEL = ~/riscv/ise/bonfire/papilio_pro_dram_toplevel.bit > PLATFORMDIR=../platform > > LINKDEF?=$(PLATFORMDIR)/$(PLATFORM)/firmware.ld > > TARGET_CFLAGS += -march=$(ARCH) -mabi=$(ABI) -Wall -Os -g > -fomit-frame-pointer \ > -ffreestanding -fno-builtin \ > -Wall -Werror=implicit-function-declaration \ > -D$(PLATFORM) > > ifeq ($(SIMULATOR), 1) > TARGET_CFLAGS+=-DSIMULATOR > endif > > TARGET_CFLAGS+=-I$(PLATFORMDIR) -I$(PLATFORMDIR)/$(PLATFORM) -I../riscv > > # If we wish to build with no newlib > #TARGET_LDFLAGS += -march=$(ARCH) -mabi=$(ABI) -nostartfiles \ > -Wl,-m,elf32lriscv,--wrap=malloc,--wrap=sbrk --specs=nosys.specs > -Wl,-T$(LINKDEF) \ > -Wl,--gc-sections > > TARGET_LDFLAGS += -march=$(ARCH) -mabi=$(ABI) -nostartfiles \ > -Wl,-m,elf32lriscv,--wrap=_srand,--wrap=_rand --specs=nano.specs > -Wl,-Map=output.map,-T$(LINKDEF) \ > -Wl,--gc-sections > > all: sim_hello.hex memtest.hex nanotest.hex > > %.o : %.S > $(TARGET_CC) $(TARGET_CFLAGS) -c $< > > %.o : %.c > $(TARGET_CC) $(TARGET_CFLAGS) -c $< > > %.hex : %.elf > $(TARGET_OBJCOPY) -S -O binary $< $(basename $@).bin > $(HEXDUMP) -v -e '1/4 "%08x\n"' $(basename $@).bin >$@ > $(TARGET_PREFIX)-objdump -S -d $< >$(basename $@).lst > #$(TARGET_PREFIX)-objdump -D $< >$(basename $@).S > $(TARGET_PREFIX)-objdump -s $< >$(basename $@).dmp > $(TARGET_PREFIX)-size $< > > #sbrk.o: libwrap/sbrk.c > # $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c libwrap/sbrk.c > > rand.o: libwrap/rand.c > $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c libwrap/rand.c > > uart.o: uart.c > $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c uart.c > > #sim_hello.o : sim_hello.c > # $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c sim_hello.c > > sim_hello.elf: start.o uart.o sim_hello.o snprintf.o console.o rand.o > $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o sim_hello.o snprintf.o > console.o rand.o > > #memtest.elf: start.o uart.o memtest.o snprintf.o console.o mempattern.o > sbrk.o > # $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o memtest.o snprintf.o > console.o mempattern.o sbrk.o > > #nanotest.elf: start.o uart.o nanotest.o snprintf.o console.o mempattern.o > sbrk.o > # $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o nanotest.o snprintf.o > console.o mempattern.o sbrk.o > > #jump0.elf : jump0.S > # $(TARGET_LD) -o $@ -march=RV32IM -nostartfiles -Wl,-T$(BOOTLINK) $< > > clean: > rm -f *.o > ---------------------------------------------------------------------------------------------.h> > #include > > //#include > //#include > #include > #include > #include > #include "bonfire.h" > #include "uart.h" > #include "bonfire_gpio.h" > #include "mem_rw.h" > #include "console.h" > > extern void* sbrk(incr); > > > // ======================================== > // Main function > // ======================================== > int main() { > > setBaudRate(PLATFORM_BAUDRATE); > > caddr_t *ptr = sbrk(0); > // code never returns from sbrk > if (ptr == (void *)-1) { > printk("Failed to allocate memory\r\n"); > } > else { > printk("Allocated memory at : %p\r\n", (void *) &ptr); > } > return 0; > } > ------------------------------------------------------------------------------------ > --- Makefile > -------------------------------------------------------------------- > > .PHONY: all clean > > ARCH ?= rv32ia > ABI=ilp32 > PLATFORM ?= S100_T35 > > #TARGET_PREFIX ?= riscv32-unknown-linux-gnu > TARGET_PREFIX ?= riscv32-unknown-elf > TARGET_CC := $(TARGET_PREFIX)-gcc > TARGET_LD := $(TARGET_PREFIX)-gcc > TARGET_SIZE := $(TARGET_PREFIX)-size > TARGET_OBJCOPY := $(TARGET_PREFIX)-objcopy > HEXDUMP ?= hexdump > DATA2MEM = /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/data2mem > > #PROJROOT = ../../.. > #TOPLEVEL = ~/riscv/ise/bonfire/papilio_pro_dram_toplevel.bit > PLATFORMDIR=../platform > > LINKDEF?=$(PLATFORMDIR)/$(PLATFORM)/firmware.ld > > TARGET_CFLAGS += -march=$(ARCH) -mabi=$(ABI) -Wall -Os -g > -fomit-frame-pointer \ > -ffreestanding -fno-builtin \ > -Wall -Werror=implicit-function-declaration \ > -D$(PLATFORM) > > ifeq ($(SIMULATOR), 1) > TARGET_CFLAGS+=-DSIMULATOR > endif > > TARGET_CFLAGS+=-I$(PLATFORMDIR) -I$(PLATFORMDIR)/$(PLATFORM) -I../riscv > > # If we wish to build with no newlib > #TARGET_LDFLAGS += -march=$(ARCH) -mabi=$(ABI) -nostartfiles \ > -Wl,-m,elf32lriscv,--wrap=malloc,--wrap=sbrk --specs=nosys.specs > -Wl,-T$(LINKDEF) \ > -Wl,--gc-sections > > TARGET_LDFLAGS += -march=$(ARCH) -mabi=$(ABI) -nostartfiles \ > -Wl,-m,elf32lriscv,--wrap=_srand,--wrap=_rand --specs=nano.specs > -Wl,-Map=output.map,-T$(LINKDEF) \ > -Wl,--gc-sections > > all: sim_hello.hex memtest.hex nanotest.hex > > %.o : %.S > $(TARGET_CC) $(TARGET_CFLAGS) -c $< > > %.o : %.c > $(TARGET_CC) $(TARGET_CFLAGS) -c $< > > %.hex : %.elf > $(TARGET_OBJCOPY) -S -O binary $< $(basename $@).bin > $(HEXDUMP) -v -e '1/4 "%08x\n"' $(basename $@).bin >$@ > $(TARGET_PREFIX)-objdump -S -d $< >$(basename $@).lst > #$(TARGET_PREFIX)-objdump -D $< >$(basename $@).S > $(TARGET_PREFIX)-objdump -s $< >$(basename $@).dmp > $(TARGET_PREFIX)-size $< > > #sbrk.o: libwrap/sbrk.c > # $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c libwrap/sbrk.c > > rand.o: libwrap/rand.c > $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c libwrap/rand.c > > uart.o: uart.c > $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c uart.c > > #sim_hello.o : sim_hello.c > # $(TARGET_CC) $(TARGET_CFLAGS) -DSIM -c sim_hello.c > > sim_hello.elf: start.o uart.o sim_hello.o snprintf.o console.o rand.o > $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o sim_hello.o snprintf.o > console.o rand.o > > #memtest.elf: start.o uart.o memtest.o snprintf.o console.o mempattern.o > sbrk.o > # $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o memtest.o snprintf.o > console.o mempattern.o sbrk.o > > #nanotest.elf: start.o uart.o nanotest.o snprintf.o console.o mempattern.o > sbrk.o > # $(TARGET_LD) -o $@ $(TARGET_LDFLAGS) start.o uart.o nanotest.o snprintf.o > console.o mempattern.o sbrk.o > > #jump0.elf : jump0.S > # $(TARGET_LD) -o $@ -march=RV32IM -nostartfiles -Wl,-T$(BOOTLINK) $< > > clean: > rm -f *.o > --------------------------------------------------------------------------------------------- -- Dave Nadler, USA East Coast voice (978) 263-0097,drn@nadler.com, Skype Dave.Nadler1 --------------wxIQ2nSWEM3I0eMMnNqzy0C2--