* [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality
@ 2022-08-24 10:18 Victor L. Do Nascimento
2022-08-24 10:27 ` [PATCH v3 1/8] newlib: libc: define M-profile PACBTI-enablement macros Victor L. Do Nascimento
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:18 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This patch series modifies hand-written assembly files for Arm targets,
conditionally enabling branch target identification as well as address
return signature and verification based on Armv8.1-M Pointer
Authentication [1] using ACLE feature test macros at compile-time [2].
The incorportaion of PACBTI functionality in function prologues/
epilogues is dictated by the arguments passed to the
`-mbranch-protection' flag at the time of Newlib compilation.
Regression tested on arm-none-eabi with and without MVE extension and
for Newlib and Newlib-nano.
[1]
<https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/101028/0012/5--Feature-test-macros>
Regards,
Victor
Victor Do Nascimento (8):
newlib: libc: define M-profile PACBTI-enablement macros
newlib: libc: strcmp M-profile PACBTI-enablement
newlib: libc: strlen M-profile PACBTI-enablement
newlib: libc: memchr M-profile PACBTI-enablement
newlib: libc: memcpy M-profile PACBTI-enablement
newlib: libc: setjmp/longjmp M-profile PACBTI-enablement
newlib: libc: aeabi_memmove M-profile PACBTI-enablement
newlib: libc: aeabi_memset M-profile PACBTI-enablement
.../libc/machine/arm/aeabi_memmove-thumb2.S | 15 +-
newlib/libc/machine/arm/aeabi_memset-thumb2.S | 12 +-
newlib/libc/machine/arm/arm_asm.h | 130 ++++++++++++++++++
newlib/libc/machine/arm/memchr.S | 34 ++++-
newlib/libc/machine/arm/memcpy-armv7m.S | 35 +++--
newlib/libc/machine/arm/setjmp.S | 33 ++++-
newlib/libc/machine/arm/strcmp-arm-tiny.S | 8 +-
newlib/libc/machine/arm/strcmp-armv7.S | 42 ++++--
newlib/libc/machine/arm/strcmp-armv7m.S | 24 ++--
newlib/libc/machine/arm/strlen-armv7.S | 16 ++-
newlib/libc/machine/arm/strlen-thumb2-Os.S | 14 +-
11 files changed, 301 insertions(+), 62 deletions(-)
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/8] newlib: libc: define M-profile PACBTI-enablement macros
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
@ 2022-08-24 10:27 ` Victor L. Do Nascimento
2022-08-24 10:30 ` [PATCH v3 2/8] newlib: libc: strcmp M-profile PACBTI-enablement Victor L. Do Nascimento
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:27 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This patch augments the arm_asm.h header file to provide support for
PACBTI enablement via macros for hand-written assembly functions,
updating both prologues/epilogues as well as cfi-related directives
depending on the compile-time mbranch-protection argument values.
It defines the following preprocessor macros:
* HAVE_PAC_LEAF: Indicates whether pac-signing has been requested for
leaf functions.
* PAC_LEAF_PUSH_IP: Whether leaf functions should push the pac code
to the stack irrespective of whether the ip register is clobbered in
the function or not.
* PAC_CFI_ADJUST: Given values for the above two parameters, this
holds the calculated offset applied to default CFI address/offset
values as a consequence of potentially pushing the pac-code to the
stack.
It also defines the following assembler macros:
* prologue: In addition to pushing any callee-saved registers onto
the stack, it generates any requested pacbti instructions.
Pushed registers are specified via the optional `first', `last' and
`savepac' macro argument parameters.
when a single register number is provided, it pushes that
register. When two register numbers are provided, they specify a
range to save. If savepac is non-zero, the ip register is also
saved.
For example:
prologue savepac=1 -> push {ip}
prologue 1 -> push {r1}
prologue 1 savepac=1 -> push {r1, ip}
prologue 1 4 -> push {r1-r4}
prologue 1 4 savepac=1 -> push {r1-r4, ip}
* epilogue: pops registers off the stack and emits pac key signing
instruction if requested. The optional `first', `last' and
`savepac' function as per the prologue macro, generating a pop
instead of push instruction.
* cfisavelist - prologue macro helper function, generating
necessary .cfi_offset directives associated with push instruction.
Therefore, the net effect of calling `prologue 1 2 savepac=1' is
to generate the following:
push {r1-r2, ip}
.cfi_adjust_cfa_offset 12
.cfi_offset 143, -12
.cfi_offset 2, -8
.cfi_offset 1, -4
* cfirestorelist - epilogue macro helper function, emitting
.cfi_restore instructions prior to resetting the cfa offset. As
such, calling `epilogue 1 2 savepac=1' will produce:
pop {r1-r2, ip}
.cfi_restore 143
.cfi_restore 2
.cfi_restore 1
.cfi_def_cfa_offset 0
Regards,
Victor
---
newlib/libc/machine/arm/arm_asm.h | 130 ++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/newlib/libc/machine/arm/arm_asm.h b/newlib/libc/machine/arm/arm_asm.h
index 2708057de..d314094c9 100644
--- a/newlib/libc/machine/arm/arm_asm.h
+++ b/newlib/libc/machine/arm/arm_asm.h
@@ -60,4 +60,134 @@
# define _ISA_THUMB_1
#endif
+/* Check whether leaf function PAC signing has been requested in the
+ -mbranch-protect compile-time option. */
+#define LEAF_PROTECT_BIT 2
+
+#ifdef __ARM_FEATURE_PAC_DEFAULT
+# define HAVE_PAC_LEAF \
+ __ARM_FEATURE_PAC_DEFAULT & (1 << LEAF_PROTECT_BIT)
+#else
+# define HAVE_PAC_LEAF 0
+#endif
+
+/* Provide default parameters for PAC-code handling in leaf-functions. */
+#ifndef PAC_LEAF_PUSH_IP
+# define PAC_LEAF_PUSH_IP 0
+#endif
+
+#if HAVE_PAC_LEAF
+# if PAC_LEAF_PUSH_IP
+# define PAC_CFI_ADJ 4
+# else
+# define PAC_CFI_ADJ 0
+# endif /* PAC_LEAF_PUSH_IP*/
+#else
+# undef PAC_LEAF_PUSH_IP
+# define PAC_LEAF_PUSH_IP 0
+# define PAC_CFI_ADJ 0
+#endif /* HAVE_PAC_LEAF */
+
+#ifdef __ASSEMBLER__
+/* Emit .cfi_restore directives for a consecutive sequence of registers. */
+ .macro cfirestorelist first, last
+ .cfi_restore \last
+ .if \last-\first
+ cfirestorelist \first, \last-1
+ .endif
+ .endm
+
+/* Emit .cfi_offset directives for a consecutive sequence of registers. */
+ .macro cfisavelist first, last, index=1
+ .cfi_offset \last, -4*(\index) - PAC_CFI_ADJ
+ .if \last-\first
+ cfisavelist \first, \last-1, \index+1
+ .endif
+ .endm
+
+/* Create a prologue entry sequence handling PAC/BTI, if required and emitting
+ CFI directives for generated PAC code and any pushed registers. */
+ .macro prologue first=-1, last=-1, savepac=PAC_LEAF_PUSH_IP
+#if HAVE_PAC_LEAF
+#if __ARM_FEATURE_BTI_DEFAULT
+ pacbti ip, lr, sp
+#else
+ pac ip, lr, sp
+#endif /* __ARM_FEATURE_BTI_DEFAULT */
+ .cfi_register 143, 12
+#else
+#if __ARM_FEATURE_BTI_DEFAULT
+ bti
+#endif /* __ARM_FEATURE_BTI_DEFAULT */
+#endif /* HAVE_PAC_LEAF */
+ .if \first != -1
+ .if \last != -1
+ .if \savepac
+ push {r\first-r\last, ip}
+ .cfi_adjust_cfa_offset ((\last-\first)+1)*4 + PAC_CFI_ADJ
+ .cfi_offset 143, -PAC_CFI_ADJ
+ cfisavelist \first, \last
+ .else
+ push {r\first-r\last}
+ .cfi_adjust_cfa_offset ((\last-\first)+1)*4
+ cfisavelist \first, \last
+ .endif
+ .else
+ .if \savepac
+ push {r\first, ip}
+ .cfi_adjust_cfa_offset 4 + PAC_CFI_ADJ
+ .cfi_offset 143, -PAC_CFI_ADJ
+ cfisavelist \first, \first
+ .else // !\savepac
+ push {r\first}
+ .cfi_adjust_cfa_offset PAC_CFI_ADJ
+ cfisavelist \first, \first
+ .endif
+ .endif
+ .else // \first == -1
+ .if \savepac
+ push {ip}
+ .cfi_adjust_cfa_offset PAC_CFI_ADJ
+ .cfi_offset 143, -PAC_CFI_ADJ
+ .endif
+ .endif
+ .endm
+
+/* Create an epilogue exit sequence handling PAC/BTI, if required and emitting
+ CFI directives for all restored registers. */
+ .macro epilogue first=-1, last=-1, savepac=PAC_LEAF_PUSH_IP
+ .if \first != -1
+ .if \last != -1
+ .if \savepac
+ pop {r\first-r\last, ip}
+ .cfi_restore 143
+ cfirestorelist \first, \last
+ .else
+ pop {r\first-r\last}
+ cfirestorelist \first, \last
+ .endif
+ .else
+ .if \savepac
+ pop {r\first, ip}
+ .cfi_restore 143
+ cfirestorelist \first, \first
+ .else
+ pop {r\first}
+ cfirestorelist \first, \first
+ .endif
+ .endif
+ .else
+ .if \savepac
+ pop {ip}
+ .cfi_restore 143
+ .endif
+ .endif
+ .cfi_def_cfa_offset 0
+#if HAVE_PAC_LEAF
+ aut ip, lr, sp
+#endif /* HAVE_PAC_LEAF */
+ bx lr
+ .endm
+#endif /* __ASSEMBLER__ */
+
#endif /* ARM_ASM__H */
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/8] newlib: libc: strcmp M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
2022-08-24 10:27 ` [PATCH v3 1/8] newlib: libc: define M-profile PACBTI-enablement macros Victor L. Do Nascimento
@ 2022-08-24 10:30 ` Victor L. Do Nascimento
2022-08-24 10:33 ` [PATCH v3 3/8] newlib: libc: strlen " Victor L. Do Nascimento
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:30 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
This patch enables PACBTI for all relevant variants of strcmp:
* Newlib for armv8.1-m.main+pacbti
* Newlib for armv8.1-m.main+pacbti+mve
* Newlib-nano
Regards,
Victor
---
newlib/libc/machine/arm/strcmp-arm-tiny.S | 8 ++++-
newlib/libc/machine/arm/strcmp-armv7.S | 42 +++++++++++++++--------
newlib/libc/machine/arm/strcmp-armv7m.S | 24 ++++++-------
3 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/newlib/libc/machine/arm/strcmp-arm-tiny.S b/newlib/libc/machine/arm/strcmp-arm-tiny.S
index 607a41daf..0bd2a2e6e 100644
--- a/newlib/libc/machine/arm/strcmp-arm-tiny.S
+++ b/newlib/libc/machine/arm/strcmp-arm-tiny.S
@@ -29,10 +29,14 @@
/* Tiny version of strcmp in ARM state. Used only when optimizing
for size. Also supports Thumb-2. */
+#include "arm_asm.h"
+
.syntax unified
def_fn strcmp
+ .fnstart
.cfi_sections .debug_frame
.cfi_startproc
+ prologue
1:
ldrb r2, [r0], #1
ldrb r3, [r1], #1
@@ -42,6 +46,8 @@ def_fn strcmp
beq 1b
2:
subs r0, r2, r3
- bx lr
+ epilogue
.cfi_endproc
+ .cantunwind
+ .fnend
.size strcmp, . - strcmp
diff --git a/newlib/libc/machine/arm/strcmp-armv7.S b/newlib/libc/machine/arm/strcmp-armv7.S
index 2f93bfb73..5bd27cb9c 100644
--- a/newlib/libc/machine/arm/strcmp-armv7.S
+++ b/newlib/libc/machine/arm/strcmp-armv7.S
@@ -45,6 +45,8 @@
.thumb
.syntax unified
+#include "arm_asm.h"
+
/* Parameters and result. */
#define src1 r0
#define src2 r1
@@ -91,8 +93,9 @@
ldrd r4, r5, [sp], #16
.cfi_restore 4
.cfi_restore 5
+ .cfi_adjust_cfa_offset -16
sub result, result, r1, lsr #24
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
#else
/* To use the big-endian trick we'd have to reverse all three words.
that's slower than this approach. */
@@ -112,22 +115,28 @@
ldrd r4, r5, [sp], #16
.cfi_restore 4
.cfi_restore 5
+ .cfi_adjust_cfa_offset -16
sub result, result, r1
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
#endif
.endm
+
.text
.p2align 5
+ .fnstart
+ .cfi_sections .debug_frame
+ .cfi_startproc
.Lstrcmp_start_addr:
#ifndef STRCMP_NO_PRECHECK
.Lfastpath_exit:
sub r0, r2, r3
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
nop
#endif
def_fn strcmp
+ prologue savepac=HAVE_PAC_LEAF
#ifndef STRCMP_NO_PRECHECK
ldrb r2, [src1]
ldrb r3, [src2]
@@ -136,16 +145,14 @@ def_fn strcmp
cmpcs r2, r3
bne .Lfastpath_exit
#endif
- .cfi_sections .debug_frame
- .cfi_startproc
strd r4, r5, [sp, #-16]!
- .cfi_def_cfa_offset 16
- .cfi_offset 4, -16
- .cfi_offset 5, -12
+ .cfi_adjust_cfa_offset 16
+ .cfi_offset 4, -(16+PAC_CFI_ADJ)
+ .cfi_offset 5, -(12+PAC_CFI_ADJ)
orr tmp1, src1, src2
strd r6, r7, [sp, #8]
- .cfi_offset 6, -8
- .cfi_offset 7, -4
+ .cfi_offset 6, -(8+PAC_CFI_ADJ)
+ .cfi_offset 7, -(4+PAC_CFI_ADJ)
mvn const_m1, #0
lsl r2, tmp1, #29
cbz r2, .Lloop_aligned8
@@ -270,7 +277,6 @@ def_fn strcmp
ldr data1, [src1], #4
beq .Laligned_m2
bcs .Laligned_m1
-
#ifdef STRCMP_NO_PRECHECK
ldrb data2, [src2, #1]
uxtb tmp1, data1, ror #BYTE1_OFFSET
@@ -314,7 +320,8 @@ def_fn strcmp
mov result, tmp1
ldr r4, [sp], #16
.cfi_restore 4
- bx lr
+ .cfi_adjust_cfa_offset -16
+ epilogue savepac=HAVE_PAC_LEAF
#ifndef STRCMP_NO_PRECHECK
.Laligned_m1:
@@ -364,8 +371,9 @@ def_fn strcmp
/* R6/7 Not used in this sequence. */
.cfi_restore 6
.cfi_restore 7
+ .cfi_adjust_cfa_offset -16
neg result, result
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
6:
.cfi_restore_state
@@ -441,7 +449,8 @@ def_fn strcmp
/* R6/7 not used in this sequence. */
.cfi_restore 6
.cfi_restore 7
- bx lr
+ .cfi_adjust_cfa_offset -16
+ epilogue savepac=HAVE_PAC_LEAF
.Lstrcmp_tail:
.cfi_restore_state
@@ -463,7 +472,10 @@ def_fn strcmp
/* R6/7 not used in this sequence. */
.cfi_restore 6
.cfi_restore 7
+ .cfi_adjust_cfa_offset -16
sub result, result, data2, lsr #24
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
.cfi_endproc
+ .cantunwind
+ .fnend
.size strcmp, . - .Lstrcmp_start_addr
diff --git a/newlib/libc/machine/arm/strcmp-armv7m.S b/newlib/libc/machine/arm/strcmp-armv7m.S
index cdb4912df..989886574 100644
--- a/newlib/libc/machine/arm/strcmp-armv7m.S
+++ b/newlib/libc/machine/arm/strcmp-armv7m.S
@@ -29,6 +29,8 @@
/* Very similar to the generic code, but uses Thumb2 as implemented
in ARMv7-M. */
+#include "arm_asm.h"
+
/* Parameters and result. */
#define src1 r0
#define src2 r1
@@ -44,8 +46,10 @@
.thumb
.syntax unified
def_fn strcmp
+ .fnstart
.cfi_sections .debug_frame
.cfi_startproc
+ prologue savepac=HAVE_PAC_LEAF
eor tmp1, src1, src2
tst tmp1, #3
/* Strings not at same byte offset from a word boundary. */
@@ -106,7 +110,7 @@ def_fn strcmp
lsrs result, result, #24
subs result, result, data2
#endif
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
#if 0
@@ -214,12 +218,12 @@ def_fn strcmp
cmpcs data1, data2
beq .Lstrcmp_unaligned
sub result, data1, data2
- bx lr
+ epilogue savepac=HAVE_PAC_LEAF
2:
stmfd sp!, {r5}
- .cfi_def_cfa_offset 4
- .cfi_offset 5, -4
+ .cfi_adjust_cfa_offset 4
+ .cfi_offset 5, -(4+PAC_CFI_ADJ)
ldr data1, [src1], #4
and tmp2, src2, #3
@@ -353,10 +357,7 @@ def_fn strcmp
.Lstrcmp_done_equal:
mov result, #0
.cfi_remember_state
- ldmfd sp!, {r5}
- .cfi_restore 5
- .cfi_def_cfa_offset 0
- bx lr
+ epilogue 5 savepac=HAVE_PAC_LEAF
.Lstrcmp_tail:
.cfi_restore_state
@@ -370,9 +371,8 @@ def_fn strcmp
S2LOEQ data2, data2, #8
beq .Lstrcmp_tail
sub result, r2, result
- ldmfd sp!, {r5}
- .cfi_restore 5
- .cfi_def_cfa_offset 0
- bx lr
+ epilogue 5 savepac=HAVE_PAC_LEAF
.cfi_endproc
+ .cantunwind
+ .fnend
.size strcmp, . - strcmp
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/8] newlib: libc: strlen M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
2022-08-24 10:27 ` [PATCH v3 1/8] newlib: libc: define M-profile PACBTI-enablement macros Victor L. Do Nascimento
2022-08-24 10:30 ` [PATCH v3 2/8] newlib: libc: strcmp M-profile PACBTI-enablement Victor L. Do Nascimento
@ 2022-08-24 10:33 ` Victor L. Do Nascimento
2022-08-24 10:34 ` [PATCH v3 4/8] newlib: libc: memchr " Victor L. Do Nascimento
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:33 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
This patch enables PACBTI for all relevant variants of strlen:
* Newlib for armv8.1-m.main+pacbti
* Newlib for armv8.1-m.main+pacbti+mve
* Newlib-nano
Regards,
Victor
---
newlib/libc/machine/arm/strlen-armv7.S | 16 +++++++++++++---
newlib/libc/machine/arm/strlen-thumb2-Os.S | 14 +++++++++++---
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/newlib/libc/machine/arm/strlen-armv7.S b/newlib/libc/machine/arm/strlen-armv7.S
index f3dda0d60..1ec6398cf 100644
--- a/newlib/libc/machine/arm/strlen-armv7.S
+++ b/newlib/libc/machine/arm/strlen-armv7.S
@@ -59,6 +59,7 @@
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#include "acle-compat.h"
+#include "arm_asm.h"
.macro def_fn f p2align=0
.text
@@ -78,7 +79,11 @@
/* This code requires Thumb. */
#if __ARM_ARCH_PROFILE == 'M'
+#if __ARM_ARCH >= 8
+ /* keep config inherited from -march=. */
+#else
.arch armv7e-m
+#endif /* if __ARM_ARCH >= 8 */
#else
.arch armv6t2
#endif
@@ -100,8 +105,10 @@
#define tmp2 r5
def_fn strlen p2align=6
+ .fnstart
+ .cfi_startproc
+ prologue 4 5 savepac=HAVE_PAC_LEAF
pld [srcin, #0]
- strd r4, r5, [sp, #-8]!
bic src, srcin, #7
mvn const_m1, #0
ands tmp1, srcin, #7 /* (8 - bytes) to alignment. */
@@ -159,9 +166,9 @@ def_fn strlen p2align=6
rev data1a, data1a
#endif
clz data1a, data1a
- ldrd r4, r5, [sp], #8
add result, result, data1a, lsr #3 /* Bits -> Bytes. */
- bx lr
+ epilogue 4 5 savepac=HAVE_PAC_LEAF
+
.Lmisaligned8:
ldrd data1a, data1b, [src]
@@ -177,4 +184,7 @@ def_fn strlen p2align=6
movne data1a, const_m1
mov const_0, #0
b .Lstart_realigned
+ .cfi_endproc
+ .cantunwind
+ .fnend
.size strlen, . - strlen
diff --git a/newlib/libc/machine/arm/strlen-thumb2-Os.S b/newlib/libc/machine/arm/strlen-thumb2-Os.S
index 961f41a0a..a46db573c 100644
--- a/newlib/libc/machine/arm/strlen-thumb2-Os.S
+++ b/newlib/libc/machine/arm/strlen-thumb2-Os.S
@@ -25,6 +25,7 @@
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#include "acle-compat.h"
+#include "arm_asm.h"
.macro def_fn f p2align=0
.text
@@ -33,8 +34,9 @@
.type \f, %function
\f:
.endm
-
-#if __ARM_ARCH_ISA_THUMB >= 2 && __ARM_ARCH >= 7
+#if __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH >= 8
+ /* keep config inherited from -march=. */
+#elif __ARM_ARCH_ISA_THUMB >= 2 && __ARM_ARCH >= 7
.arch armv7
#else
.arch armv6t2
@@ -44,11 +46,17 @@
.syntax unified
def_fn strlen p2align=1
+ .fnstart
+ .cfi_startproc
+ prologue
mov r3, r0
1: ldrb.w r2, [r3], #1
cmp r2, #0
bne 1b
subs r0, r3, r0
subs r0, #1
- bx lr
+ epilogue
+ .cfi_endproc
+ .cantunwind
+ .fnend
.size strlen, . - strlen
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 4/8] newlib: libc: memchr M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
` (2 preceding siblings ...)
2022-08-24 10:33 ` [PATCH v3 3/8] newlib: libc: strlen " Victor L. Do Nascimento
@ 2022-08-24 10:34 ` Victor L. Do Nascimento
2022-08-24 10:36 ` [PATCH v3 5/8] newlib: libc: memcpy " Victor L. Do Nascimento
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:34 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
Regards,
Victor
---
newlib/libc/machine/arm/memchr.S | 34 +++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/newlib/libc/machine/arm/memchr.S b/newlib/libc/machine/arm/memchr.S
index 1a4c6512c..2401020c0 100644
--- a/newlib/libc/machine/arm/memchr.S
+++ b/newlib/libc/machine/arm/memchr.S
@@ -76,6 +76,7 @@
.syntax unified
#include "acle-compat.h"
+#include "arm_asm.h"
@ NOTE: This ifdef MUST match the one in memchr-stub.c
#if defined (__ARM_NEON__) || defined (__ARM_NEON)
@@ -267,10 +268,14 @@ memchr:
#elif __ARM_ARCH_ISA_THUMB >= 2 && defined (__ARM_FEATURE_DSP)
#if __ARM_ARCH_PROFILE == 'M'
- .arch armv7e-m
+#if __ARM_ARCH >= 8
+ /* keep config inherited from -march=. */
#else
- .arch armv6t2
-#endif
+ .arch armv7e-m
+#endif /* __ARM_ARCH >= 8 */
+#else
+ .arch armv6t2
+#endif /* __ARM_ARCH_PROFILE == 'M' */
@ this lets us check a flag in a 00/ff byte easily in either endianness
#ifdef __ARMEB__
@@ -287,11 +292,14 @@ memchr:
.p2align 4,,15
.global memchr
.type memchr,%function
+ .fnstart
+ .cfi_startproc
memchr:
@ r0 = start of memory to scan
@ r1 = character to look for
@ r2 = length
@ returns r0 = pointer to character or NULL if not found
+ prologue
and r1,r1,#0xff @ Don't trust the caller to pass a char
cmp r2,#16 @ If short don't bother with anything clever
@@ -313,6 +321,11 @@ memchr:
10:
@ We are aligned, we know we have at least 8 bytes to work with
push {r4,r5,r6,r7}
+ .cfi_adjust_cfa_offset 16
+ .cfi_offset 4, -(16+PAC_CFI_ADJ)
+ .cfi_offset 5, -(12+PAC_CFI_ADJ)
+ .cfi_offset 6, -(8+PAC_CFI_ADJ)
+ .cfi_offset 7, -(4+PAC_CFI_ADJ)
orr r1, r1, r1, lsl #8 @ expand the match word across all bytes
orr r1, r1, r1, lsl #16
bic r4, r2, #7 @ Number of double words to work with * 8
@@ -334,6 +347,11 @@ memchr:
bne 15b @ (Flags from the subs above)
pop {r4,r5,r6,r7}
+ .cfi_restore 7
+ .cfi_restore 6
+ .cfi_restore 5
+ .cfi_restore 4
+ .cfi_adjust_cfa_offset -16
and r1,r1,#0xff @ r1 back to a single character
and r2,r2,#7 @ Leave the count remaining as the number
@ after the double words have been done
@@ -350,11 +368,11 @@ memchr:
40:
movs r0,#0 @ not found
- bx lr
+ epilogue
50:
subs r0,r0,#1 @ found
- bx lr
+ epilogue
60: @ We're here because the fast path found a hit
@ now we have to track down exactly which word it was
@@ -378,9 +396,11 @@ memchr:
addeq r0,r0,#1
61:
- pop {r4,r5,r6,r7}
subs r0,r0,#1
- bx lr
+ epilogue 4 7
+ .cfi_endproc
+ .cantunwind
+ .fnend
#else
/* Defined in memchr-stub.c. */
#endif
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 5/8] newlib: libc: memcpy M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
` (3 preceding siblings ...)
2022-08-24 10:34 ` [PATCH v3 4/8] newlib: libc: memchr " Victor L. Do Nascimento
@ 2022-08-24 10:36 ` Victor L. Do Nascimento
2022-08-24 10:38 ` [PATCH v3 6/8] newlib: libc: setjmp/longjmp " Victor L. Do Nascimento
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:36 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
Regards,
Victor
---
newlib/libc/machine/arm/memcpy-armv7m.S | 35 +++++++++++++++++--------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/newlib/libc/machine/arm/memcpy-armv7m.S b/newlib/libc/machine/arm/memcpy-armv7m.S
index c8bff36f6..793989d36 100644
--- a/newlib/libc/machine/arm/memcpy-armv7m.S
+++ b/newlib/libc/machine/arm/memcpy-armv7m.S
@@ -46,6 +46,8 @@
__OPT_BIG_BLOCK_SIZE: Size of big block in words. Default to 64.
__OPT_MID_BLOCK_SIZE: Size of big block in words. Default to 16.
*/
+#include "arm_asm.h"
+
#ifndef __OPT_BIG_BLOCK_SIZE
#define __OPT_BIG_BLOCK_SIZE (4 * 16)
#endif
@@ -85,6 +87,8 @@
.global memcpy
.thumb
.thumb_func
+ .fnstart
+ .cfi_startproc
.type memcpy, %function
memcpy:
@ r0: dst
@@ -93,10 +97,11 @@ memcpy:
#ifdef __ARM_FEATURE_UNALIGNED
/* In case of UNALIGNED access supported, ip is not used in
function body. */
+ prologue savepac=HAVE_PAC_LEAF
mov ip, r0
#else
- push {r0}
-#endif
+ prologue 0 savepac=HAVE_PAC_LEAF
+#endif /* __ARM_FEATURE_UNALIGNED */
orr r3, r1, r0
ands r3, r3, #3
bne .Lmisaligned_copy
@@ -135,13 +140,13 @@ memcpy:
ldr r3, [r1], #4
str r3, [r0], #4
END_UNROLL
-#else /* __ARM_ARCH_7M__ */
+#else
ldr r3, [r1, \offset]
str r3, [r0, \offset]
END_UNROLL
adds r0, __OPT_MID_BLOCK_SIZE
adds r1, __OPT_MID_BLOCK_SIZE
-#endif
+#endif /* __ARM_ARCH_7M__ */
subs r2, __OPT_MID_BLOCK_SIZE
bhs .Lmid_block_loop
@@ -180,10 +185,10 @@ memcpy:
.Ldone:
#ifdef __ARM_FEATURE_UNALIGNED
mov r0, ip
+ epilogue savepac=HAVE_PAC_LEAF
#else
- pop {r0}
-#endif
- bx lr
+ epilogue 0 savepac=HAVE_PAC_LEAF
+#endif /* __ARM_FEATURE_UNALIGNED */
.align 2
.Lmisaligned_copy:
@@ -247,6 +252,9 @@ memcpy:
/* dst is aligned, but src isn't. Misaligned copy. */
push {r4, r5}
+ .cfi_adjust_cfa_offset 8
+ .cfi_offset 4, -(8+PAC_CFI_ADJ)
+ .cfi_offset 5, -(4+PAC_CFI_ADJ)
subs r2, #4
/* Backward r1 by misaligned bytes, to make r1 aligned.
@@ -299,6 +307,9 @@ memcpy:
adds r2, #4
subs r1, ip
pop {r4, r5}
+ .cfi_restore 4
+ .cfi_restore 5
+ .cfi_adjust_cfa_offset -8
#endif /* __ARM_FEATURE_UNALIGNED */
@@ -321,9 +332,11 @@ memcpy:
#ifdef __ARM_FEATURE_UNALIGNED
mov r0, ip
+ epilogue savepac=HAVE_PAC_LEAF
#else
- pop {r0}
-#endif
- bx lr
-
+ epilogue 0 savepac=HAVE_PAC_LEAF
+#endif /* __ARM_FEATURE_UNALIGNED */
+ .cfi_endproc
+ .cantunwind
+ .fnend
.size memcpy, .-memcpy
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 6/8] newlib: libc: setjmp/longjmp M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
` (4 preceding siblings ...)
2022-08-24 10:36 ` [PATCH v3 5/8] newlib: libc: memcpy " Victor L. Do Nascimento
@ 2022-08-24 10:38 ` Victor L. Do Nascimento
2022-08-24 10:40 ` [PATCH v3 7/8] newlib: libc: aeabi_memmove " Victor L. Do Nascimento
2022-08-24 10:41 ` [PATCH v3 8/8] newlib: libc: aeabi_memset " Victor L. Do Nascimento
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:38 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
Regards,
Victor
---
newlib/libc/machine/arm/setjmp.S | 33 ++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/newlib/libc/machine/arm/setjmp.S b/newlib/libc/machine/arm/setjmp.S
index 21d6ff9e7..4fe53cdf2 100644
--- a/newlib/libc/machine/arm/setjmp.S
+++ b/newlib/libc/machine/arm/setjmp.S
@@ -157,11 +157,15 @@ SYM (.arm_start_of.\name):
.globl SYM (\name)
TYPE (\name)
SYM (\name):
+ .fnstart
+ .cfi_startproc
PROLOGUE \name
.endm
.macro FUNC_END name
RET
+ .cfi_endproc
+ .fnend
SIZE (\name)
.endm
@@ -173,11 +177,26 @@ SYM (\name):
/* Save all the callee-preserved registers into the jump buffer. */
#ifdef __thumb2__
+#if __ARM_FEATURE_PAC_DEFAULT
+#if __ARM_FEATURE_BTI_DEFAULT
+ pacbti ip, lr, sp
+#else
+ pac ip, lr, sp
+#endif /* __ARM_FEATURE_BTI_DEFAULT */
+ .cfi_register 143, 12
+ mov a4, ip
+ mov ip, sp
+ stmea a1!, { a4, v1-v7, fp, ip, lr }
+#else
+#if __ARM_FEATURE_BTI_DEFAULT
+ bti
+#endif /* __ARM_FEATURE_BTI_DEFAULT */
mov ip, sp
stmea a1!, { v1-v7, fp, ip, lr }
+#endif /* __ARM_FEATURE_PAC_DEFAULT */
#else
stmea a1!, { v1-v7, fp, ip, sp, lr }
-#endif
+#endif /* __thumb2__ */
#if 0 /* Simulator does not cope with FP instructions yet. */
#ifndef __SOFTFP__
@@ -200,11 +219,17 @@ SYM (\name):
/* Restore the registers, retrieving the state when setjmp() was called. */
#ifdef __thumb2__
+#if __ARM_FEATURE_PAC_DEFAULT
+ ldmfd a1!, { a4, v1-v7, fp, ip, lr }
+ mov sp, ip
+ mov ip, a4
+#else
ldmfd a1!, { v1-v7, fp, ip, lr }
mov sp, ip
+#endif /* __ARM_FEATURE_PAC_DEFAULT */
#else
ldmfd a1!, { v1-v7, fp, ip, sp, lr }
-#endif
+#endif /* __thumb2__ */
#if 0 /* Simulator does not cope with FP instructions yet. */
#ifndef __SOFTFP__
@@ -220,5 +245,9 @@ SYM (\name):
#endif
moveq a1, #1
+#if __ARM_FEATURE_PAC_DEFAULT
+ aut ip, lr, sp
+#endif
+
FUNC_END longjmp
#endif
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 7/8] newlib: libc: aeabi_memmove M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
` (5 preceding siblings ...)
2022-08-24 10:38 ` [PATCH v3 6/8] newlib: libc: setjmp/longjmp " Victor L. Do Nascimento
@ 2022-08-24 10:40 ` Victor L. Do Nascimento
2022-08-24 10:41 ` [PATCH v3 8/8] newlib: libc: aeabi_memset " Victor L. Do Nascimento
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:40 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
Regards,
Victor
---
newlib/libc/machine/arm/aeabi_memmove-thumb2.S | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/newlib/libc/machine/arm/aeabi_memmove-thumb2.S b/newlib/libc/machine/arm/aeabi_memmove-thumb2.S
index e9504437b..817f0e2df 100644
--- a/newlib/libc/machine/arm/aeabi_memmove-thumb2.S
+++ b/newlib/libc/machine/arm/aeabi_memmove-thumb2.S
@@ -26,6 +26,8 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arm_asm.h"
+
.thumb
.syntax unified
.global __aeabi_memmove
@@ -33,8 +35,10 @@
ASM_ALIAS __aeabi_memmove4 __aeabi_memmove
ASM_ALIAS __aeabi_memmove8 __aeabi_memmove
__aeabi_memmove:
+ .fnstart
+ .cfi_startproc
+ prologue 4
cmp r0, r1
- push {r4}
bls 3f
adds r3, r1, r2
cmp r0, r3
@@ -48,8 +52,7 @@ __aeabi_memmove:
strb r4, [r1, #-1]!
bne 1b
2:
- pop {r4}
- bx lr
+ epilogue 4
3:
cmp r2, #0
beq 2b
@@ -60,6 +63,8 @@ __aeabi_memmove:
cmp r2, r1
strb r4, [r3, #1]!
bne 4b
- pop {r4}
- bx lr
+ epilogue 4
+ .cfi_endproc
+ .cantunwind
+ .fnend
.size __aeabi_memmove, . - __aeabi_memmove
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 8/8] newlib: libc: aeabi_memset M-profile PACBTI-enablement
2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
` (6 preceding siblings ...)
2022-08-24 10:40 ` [PATCH v3 7/8] newlib: libc: aeabi_memmove " Victor L. Do Nascimento
@ 2022-08-24 10:41 ` Victor L. Do Nascimento
7 siblings, 0 replies; 9+ messages in thread
From: Victor L. Do Nascimento @ 2022-08-24 10:41 UTC (permalink / raw)
To: newlib; +Cc: Richard.Earnshaw
Hi all,
This adds function prologue/epilogue to conditionally add BTI landing
pads and/or PAC code generation & authentication instructions depending
on compilation flags.
Regards,
Victor
---
newlib/libc/machine/arm/aeabi_memset-thumb2.S | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/newlib/libc/machine/arm/aeabi_memset-thumb2.S b/newlib/libc/machine/arm/aeabi_memset-thumb2.S
index eaca1d8d7..dec5fd74f 100644
--- a/newlib/libc/machine/arm/aeabi_memset-thumb2.S
+++ b/newlib/libc/machine/arm/aeabi_memset-thumb2.S
@@ -26,14 +26,18 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arm_asm.h"
+
.thumb
.syntax unified
.global __aeabi_memset
.type __aeabi_memset, %function
+ .fnstart
+ .cfi_startproc
ASM_ALIAS __aeabi_memset4 __aeabi_memset
ASM_ALIAS __aeabi_memset8 __aeabi_memset
__aeabi_memset:
- push {r4, r5, r6}
+ prologue 4 6
lsls r4, r0, #30
beq 10f
subs r4, r1, #1
@@ -98,10 +102,12 @@ __aeabi_memset:
cmp r3, r4
bne 8b
9:
- pop {r4, r5, r6}
- bx lr
+ epilogue 4 6
10:
mov r4, r1
mov r3, r0
b 3b
+ .cfi_endproc
+ .cantunwind
+ .fnend
.size __aeabi_memset, . - __aeabi_memset
--
2.36.1
^ permalink raw reply [flat|nested] 9+ messages in thread
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Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
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2022-08-24 10:18 [PATCH v3 0/8] Implement assembly cortex-M PACBTI functionality Victor L. Do Nascimento
2022-08-24 10:27 ` [PATCH v3 1/8] newlib: libc: define M-profile PACBTI-enablement macros Victor L. Do Nascimento
2022-08-24 10:30 ` [PATCH v3 2/8] newlib: libc: strcmp M-profile PACBTI-enablement Victor L. Do Nascimento
2022-08-24 10:33 ` [PATCH v3 3/8] newlib: libc: strlen " Victor L. Do Nascimento
2022-08-24 10:34 ` [PATCH v3 4/8] newlib: libc: memchr " Victor L. Do Nascimento
2022-08-24 10:36 ` [PATCH v3 5/8] newlib: libc: memcpy " Victor L. Do Nascimento
2022-08-24 10:38 ` [PATCH v3 6/8] newlib: libc: setjmp/longjmp " Victor L. Do Nascimento
2022-08-24 10:40 ` [PATCH v3 7/8] newlib: libc: aeabi_memmove " Victor L. Do Nascimento
2022-08-24 10:41 ` [PATCH v3 8/8] newlib: libc: aeabi_memset " Victor L. Do Nascimento
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