From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8668 invoked by alias); 31 May 2002 20:35:28 -0000 Mailing-List: contact sid-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sources.redhat.com Received: (qmail 8644 invoked from network); 31 May 2002 20:35:26 -0000 Received: from unknown (HELO touchme.toronto.redhat.com) (216.138.202.10) by sources.redhat.com with SMTP; 31 May 2002 20:35:26 -0000 Received: from tooth.toronto.redhat.com (unknown [172.16.14.29]) by touchme.toronto.redhat.com (Postfix) with ESMTP id 69300B8013; Fri, 31 May 2002 16:35:25 -0400 (EDT) Received: (from bje@localhost) by tooth.toronto.redhat.com (8.11.6/8.11.6) id g4VKZPR06659; Fri, 31 May 2002 16:35:25 -0400 From: Ben Elliston MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <15607.56973.58661.290693@tooth.toronto.redhat.com> Date: Fri, 31 May 2002 13:35:00 -0000 To: "Frank Ch. Eigler" Cc: sid@sources.redhat.com Subject: Re: CPU disassembler-memory accessor In-Reply-To: <20020529115301.C17962@redhat.com> References: <15604.59813.750421.114817@tooth.toronto.redhat.com> <20020529115301.C17962@redhat.com> X-SW-Source: 2002-q2/txt/msg00025.txt.bz2 >>>>> "FChE" == Frank Ch Eigler writes: FChE> Yes, just one. The read_disasm_memory_1 function is methinks FChE> overengineered. It doesn't need to throw exceptions, nor handle FChE> accesses of other sizes. Actually, why not just do a direct FChE> sid::bus-level read() on the accessor and do away with the FChE> read_disasm_memory* thingie altogether? Thanks for the feedback. How's this instead? Index: include/sidcpuutil.h =================================================================== RCS file: /cvs/cvsfiles/devo/sid/include/sidcpuutil.h,v retrieving revision 1.28.2.4 diff -u -p -r1.28.2.4 sidcpuutil.h --- include/sidcpuutil.h 2002/04/23 21:07:51 1.28.2.4 +++ include/sidcpuutil.h 2002/05/31 13:15:37 @@ -495,6 +495,7 @@ namespace sidutil protected: sid::bus* data_bus; sid::bus* insn_bus; + sid::bus* disassembler_bus; protected: template @@ -506,6 +507,8 @@ namespace sidutil template BigOrLittleInt write_data_memory (sid::host_int_4 pc, sid::host_int_4 address, BigOrLittleInt value) const; + bool read_disasm_memory (sid::host_int_4 address, sid::big_int_1& value) const; + // ------------------------------------------------------------------------ public: @@ -529,6 +532,8 @@ public: add_accessor ("data-memory", & this->data_bus); this->insn_bus = 0; add_accessor ("insn-memory", & this->insn_bus); + this->disassembler_bus = 0; + add_accessor ("disassembler-memory", & this->disassembler_bus); add_bus ("debugger-bus", & this->debugger_bus); // pins @@ -597,6 +602,23 @@ public: else dynamic_cast (s) << t; return s; + } + + inline bool + basic_cpu::read_disasm_memory (sid::host_int_4 address, sid::big_int_1& value) const + { + sid::bus* bus; + bus = (this->disassembler_bus) ? this->disassembler_bus : this->insn_bus; + + try + { + if (LIKELY (bus->read (address, value) == sid::bus::ok)) + return true; + } + catch (cpu_memory_fault& f) + { + return false; + } } template Index: component/cgen-cpu/compCGEN.cxx =================================================================== RCS file: /cvs/cvsfiles/devo/sid/component/cgen-cpu/compCGEN.cxx,v retrieving revision 1.66.2.5 diff -u -p -r1.66.2.5 compCGEN.cxx --- component/cgen-cpu/compCGEN.cxx 2002/04/03 18:43:36 1.66.2.5 +++ component/cgen-cpu/compCGEN.cxx 2002/05/31 13:15:35 @@ -184,10 +184,6 @@ cgen_bi_endian_cpu::cgen_read_memory(bfd { cgen_bi_endian_cpu *thisp = static_cast(info->application_data); - // We don't want to penalize the disassembler with memory latency counts, so we - // store it away here ... - host_int_8 prev_latency = thisp->total_latency; - switch (length) { #if 0 // XXX not sure if this has byte order dependancies or not case 1: @@ -204,13 +200,17 @@ cgen_bi_endian_cpu::cgen_read_memory(bfd break; #endif default: - for (int i = 0; i < length; i++) - *(myaddr + i) = thisp->read_insn_memory_1(0, memaddr + i); + { + big_int_1 value; + for (int i = 0; i < length; i++) + { + if (! thisp->read_disasm_memory (memaddr + i, value)) + return 1; + else + *(myaddr + i) = value; + } + } } - - // ... and restore it here. - thisp->total_latency = prev_latency; - return 0; } Index: component/cgen-cpu/common-xml/behavior.xml =================================================================== RCS file: /cvs/cvsfiles/devo/sid/component/cgen-cpu/common-xml/behavior.xml,v retrieving revision 1.1.10.1 diff -u -p -r1.1.10.1 behavior.xml --- component/cgen-cpu/common-xml/behavior.xml 2002/03/14 01:04:39 1.1.10.1 +++ component/cgen-cpu/common-xml/behavior.xml 2002/05/31 13:15:35 @@ -32,9 +32,12 @@

Each instruction is first fetched from memory via the insn-memory accessor, and its decoding traced if the trace-extract? attribute is - set to a true value. The decoded form may be cached - indefinitely afterwards, although this cache is flushed when the - flush-icache pin is driven.

+ set to a true value. To prevent unwanted cache side effects, + the disassembler-memory accessor can be + used and connected directly to main memory, bypassing any memory + caches. The decoded form may be cached indefinitely afterwards, + although this cache is flushed when the flush-icache + pin is driven.

The engine-type attribute specifies whether the "scache" ("semantic cache") or "pbb" ("pseudo basic Index: component/cgen-cpu/common-xml/interface.xml =================================================================== RCS file: /cvs/cvsfiles/devo/sid/component/cgen-cpu/common-xml/interface.xml,v retrieving revision 1.2.10.1 diff -u -p -r1.2.10.1 interface.xml --- component/cgen-cpu/common-xml/interface.xml 2002/03/14 01:04:39 1.2.10.1 +++ component/cgen-cpu/common-xml/interface.xml 2002/05/31 13:15:35 @@ -16,6 +16,7 @@ +