Re: modeling latency (fwd)

["Frank Ch. Eigler" <fche@redhat.com>]

Hi -

bje wrote:
: [...]
:   FChE> (ditto, to account for cache hit times & miss penalties), all the way
:   FChE> to the CPU.  (The "sid::bus::delayed" indication can finally die.)
: 
: What was the intention of the delayed indication?  [...]

It was to be a different way of representing bus latency.  Instead of
merely counting cycles, the bus::delayed indication was to tell the
bus master to yield to the target scheduler for a while, and try
again later.  There is some theoretical appeal, but implementing it
this way is too complicated.  For example, it would require making
all CPU memory access calls points abort/restartable; it would involve
the target scheduler a lot.  I believe some sid alumni had the same
ideas, but never got around to expressing them (and obviously to
implementing them).

IMO it can go away altogether.

BTW, regarding the proposed bus::status patch, it would be nice if you
could find some way of ensuring/requesting that the compiler packs the
struct into 4 bytes.  Maybe the g++ "enum foo : 16" extension, maybe
something else.

- FChE
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-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.0.6 (GNU/Linux)
Comment: For info see http://www.gnupg.org

iD8DBQE7Mdi9VZbdDOm/ZT0RAkUIAJ9U+zgxa7u/FcThN6Hs9vcvRRZrDgCdEJ1K
9ehrlze9/q6ml8Xk28FbpKo=
=bUh0
-----END PGP SIGNATURE-----