From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20437 invoked by alias); 22 Jun 2004 16:23:10 -0000 Mailing-List: contact sid-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sources.redhat.com Received: (qmail 20430 invoked from network); 22 Jun 2004 16:23:09 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org with SMTP; 22 Jun 2004 16:23:09 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i5MGN9e1029137 for ; Tue, 22 Jun 2004 12:23:09 -0400 Received: from pobox.toronto.redhat.com (pobox.toronto.redhat.com [172.16.14.4]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i5MGN9010498; Tue, 22 Jun 2004 12:23:09 -0400 Received: from touchme.toronto.redhat.com (IDENT:postfix@touchme.toronto.redhat.com [172.16.14.9]) by pobox.toronto.redhat.com (8.12.8/8.12.8) with ESMTP id i5MGN8tn008829; Tue, 22 Jun 2004 12:23:08 -0400 Received: from toenail.toronto.redhat.com (toenail.toronto.redhat.com [172.16.14.211]) by touchme.toronto.redhat.com (Postfix) with ESMTP id 92C148003A5; Tue, 22 Jun 2004 12:23:08 -0400 (EDT) Received: from toenail.toronto.redhat.com (localhost.localdomain [127.0.0.1]) by toenail.toronto.redhat.com (8.12.10/8.12.5) with ESMTP id i5MGN8C1017381; Tue, 22 Jun 2004 12:23:08 -0400 Received: (from fche@localhost) by toenail.toronto.redhat.com (8.12.10/8.12.10/Submit) id i5MGN8Tc017379; Tue, 22 Jun 2004 12:23:08 -0400 Date: Tue, 22 Jun 2004 16:23:00 -0000 From: "Frank Ch. Eigler" To: Robert Shideleff Cc: sid@sources.redhat.com Subject: Re: GDB/mapper cache problems Message-ID: <20040622162307.GF5740@redhat.com> References: <200406162156.54577.bigbob@shideleff.com> <20040622024603.GB22793@redhat.com> <200406212319.30979.bigbob@shideleff.com> <200406221208.25786.bigbob@shideleff.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Uwl7UQhJk99r8jnw" Content-Disposition: inline In-Reply-To: <200406221208.25786.bigbob@shideleff.com> User-Agent: Mutt/1.4.1i X-SW-Source: 2004-q2/txt/msg00045.txt.bz2 --Uwl7UQhJk99r8jnw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Content-length: 1237 Hi - > Alright, I figured the gdb problem. I hadn't connected the gdb yield pins= to=20 > the yield bus. gdb debugging now seems to work perfectly. OK. I believe that the C++ sid configuration engine in sid/main/dynamic is not well customized yet for the arm family of targets, so you may encounter a few such problems. Regarding interleaving the processors, what you are seeing intentional. The CPU models are parametrized to allow you to trade off speed versus accuracy. (Executing N instructions in one CPU before switching context to the rest of the sim can be significantly faster.) > I think the second part of my problem where data doesn't seem to reliably > make its way into the dual port ram is due to mapper cache.=20 The mapper cache probably does not relate to this - you probably mean something other than the little internal TLB in the memory-mapper component that helps classify incoming read/write addresses. > How can I cause a particular bus access to poke the yield net? [...] For example, you could use the hw-glue-bus-probe component: wire up one instance of it into the bus structure by mapping it at some address; use its pin outputs to trigger any desired pin-based event in the simulator. - FChE --Uwl7UQhJk99r8jnw Content-Type: application/pgp-signature Content-Disposition: inline Content-length: 189 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.3 (GNU/Linux) iD8DBQFA2FzrVZbdDOm/ZT0RAnRLAJ9cjn2GBw9y1m8SGB0kVIQo8w4y1ACggu5J JmTt4APM2aCisi56P6rNQ1M= =JzxJ -----END PGP SIGNATURE----- --Uwl7UQhJk99r8jnw--