From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6216 invoked by alias); 2 Jul 2004 18:37:40 -0000 Mailing-List: contact sid-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sources.redhat.com Received: (qmail 6169 invoked from network); 2 Jul 2004 18:37:39 -0000 Received: from unknown (HELO pine.epix.net) (199.224.64.53) by sourceware.org with SMTP; 2 Jul 2004 18:37:39 -0000 Received: from cecile.shideleff.com (hrbg-216-108-204-31-pppoe.dsl.hrbg.epix.net [216.108.204.31]) by pine.epix.net (8.12.10/2004012201/PL) with ESMTP id i62IbbWT019432 for ; Fri, 2 Jul 2004 14:37:37 -0400 (EDT) Received: from dinky.shideleff.com (dinky.shideleff.com [192.168.0.107]) by cecile.shideleff.com (Postfix) with ESMTP id 02C4B25876C for ; Fri, 2 Jul 2004 14:37:35 -0400 (EDT) From: Robert Shideleff To: sid@sources.redhat.com Subject: Level sensitive ARM interrupts Date: Fri, 02 Jul 2004 18:37:00 -0000 User-Agent: KMail/1.6.2 MIME-Version: 1.0 Content-Disposition: inline Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Message-Id: <200407021437.35768.bigbob@shideleff.com> X-Scanned-By: MIMEDefang 2.41 X-SW-Source: 2004-q3/txt/msg00003.txt.bz2 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 This patch makes arm interrupts level sensitive, as they are in hardware. T= he=20 nirq and nfiq pins are no longer callbacks, but rather simple input pins.=20 They are 'pulled' to high at processor invocation and reset. Their level is= =20 'sense()-ed' at the beginning of each step. The patch file was taken from within the sid/component/cgen-cpu/arm7t=20 directory. This is necessary for proper operation of eCos, and for the ability to mode= l=20 interrupts as they occur in actual hardware. Bob -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.4 (GNU/Linux) iD8DBQFA5atv8XjOGQDr37YRAte8AKCYZ9EYpSH0lusoyA38/KaCT81rfwCcCglg Kp6FvMyVsWcJYymMa9uHwqw=3D =3Dqqdg -----END PGP SIGNATURE-----