From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12063 invoked by alias); 16 Oct 2011 07:58:01 -0000 Received: (qmail 11972 invoked by uid 22791); 16 Oct 2011 07:57:46 -0000 X-SWARE-Spam-Status: No, hits=-1.2 required=5.0 tests=AWL,BAYES_05,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from feith1.FEITH.COM (HELO feith1.FEITH.COM) (192.251.93.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 16 Oct 2011 05:03:35 +0000 Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.4+Sun/8.12.9) with ESMTP id p9G53XRQ021585 for ; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4) with ESMTP id p9G53XSf025575 for ; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4/Submit) id p9G53XJI025574 for sid@sources.redhat.com; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) Date: Sun, 16 Oct 2011 07:58:00 -0000 From: John Wehle Message-Id: <201110160503.p9G53XJI025574@jwlab.FEITH.COM> To: sid@sources.redhat.com Subject: sid-20110801 Patch to fix cache writeback latency MIME-Version: 1.0 Content-Type: text/plain X-DCC-dmv.com-Metrics: feith1; whitelist Mailing-List: contact sid-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sourceware.org X-SW-Source: 2011-q4/txt/msg00001.txt.bz2 Currently when the SID cache component replaces a line which is dirty it writes back the data to memory. However it ignores that fact that the writeback adds to the latency causing the simulation to believe that the replacement of a dirty cache line takes the same amount of time as the replacement of a clean cache line. The enclosed patch has been tested on FreeBSD with sid configured for tomi Borealis (a processor under development by Venray Technology). ChangeLog: Sun Oct 16 00:03:43 EDT 2011 John Wehle (john@feith.com) * component/cache/cache.cxx (write_any, read_any): Latency should include the writeback of a dirty line. -- John ------------------------8<------------------------------8<--------------- --- component/cache/cache.cxx.ORIGINAL 2009-04-08 16:39:34.000000000 -0400 +++ component/cache/cache.cxx 2011-10-13 00:22:20.000000000 -0400 @@ -184,7 +182,7 @@ template bus::status cache_component::write_any (host_int_4 addr, DataType data) { - bus::status st, read_status; + bus::status st, read_status, writeback_status; if (UNLIKELY (downstream == 0)) return bus::unmapped; @@ -237,8 +235,8 @@ cache_component::write_any (host_int_4 a if (expelled_line->valid_p () && expelled_line->dirty_p ()) { // flush a dirty line being replaced - if ((st = write_line (*expelled_line)) != bus::ok) - return st; + if ((writeback_status = write_line (*expelled_line)) != bus::ok) + return writeback_status; } } else @@ -279,7 +277,7 @@ cache_component::write_any (host_int_4 a if (line) st.latency = hit_latency; else - st.latency = read_status.latency + miss_latency; + st.latency = writeback_status.latency + read_status.latency + miss_latency; return st; } @@ -287,7 +285,7 @@ template bus::status cache_component::read_any (host_int_4 addr, DataType& data) { - bus::status st, read_status; + bus::status st, read_status, writeback_status; if (UNLIKELY (downstream == 0)) return bus::unmapped; @@ -327,8 +325,8 @@ cache_component::read_any (host_int_4 ad if (expelled_line->valid_p () && expelled_line->dirty_p ()) { // flush a dirty line being replaced - if ((st = write_line (*expelled_line)) != bus::ok) - return st; + if ((writeback_status = write_line (*expelled_line)) != bus::ok) + return writeback_status; } expelled_line->set_tag (tag); if ((read_status = read_line (*expelled_line)) != bus::ok) @@ -353,7 +351,7 @@ cache_component::read_any (host_int_4 ad if (line) st.latency += hit_latency; else - st.latency = read_status.latency + miss_latency; + st.latency = writeback_status.latency + read_status.latency + miss_latency; return st; } ------------------------------------------------------------------------- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16484 invoked by alias); 16 Oct 2011 08:01:07 -0000 Received: (qmail 16477 invoked by uid 22791); 16 Oct 2011 08:01:06 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from feith1.FEITH.COM (HELO feith1.FEITH.COM) (192.251.93.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 16 Oct 2011 08:00:49 +0000 Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.4+Sun/8.12.9) with ESMTP id p9G53XRQ021585 for ; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4) with ESMTP id p9G53XSf025575 for ; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4/Submit) id p9G53XJI025574 for sid@sources.redhat.com; Sun, 16 Oct 2011 01:03:33 -0400 (EDT) Date: Tue, 01 Nov 2011 14:29:00 -0000 From: John Wehle Message-ID: <201110160503.p9G53XJI025574@jwlab.FEITH.COM> To: sid@sources.redhat.com Subject: sid-20110801 Patch to fix cache writeback latency MIME-Version: 1.0 Content-Type: text/plain X-DCC-dmv.com-Metrics: feith1; whitelist Mailing-List: contact sid-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sourceware.org X-SW-Source: 2011-q4/txt/msg00005.txt.bz2 Message-ID: <20111101142900.XxttOEm3lYlYe8xCwBRP7Relb6bct5rRx1UniF2cCNU@z> Currently when the SID cache component replaces a line which is dirty it writes back the data to memory. However it ignores that fact that the writeback adds to the latency causing the simulation to believe that the replacement of a dirty cache line takes the same amount of time as the replacement of a clean cache line. The enclosed patch has been tested on FreeBSD with sid configured for tomi Borealis (a processor under development by Venray Technology). ChangeLog: Sun Oct 16 00:03:43 EDT 2011 John Wehle (john@feith.com) * component/cache/cache.cxx (write_any, read_any): Latency should include the writeback of a dirty line. -- John ------------------------8<------------------------------8<--------------- --- component/cache/cache.cxx.ORIGINAL 2009-04-08 16:39:34.000000000 -0400 +++ component/cache/cache.cxx 2011-10-13 00:22:20.000000000 -0400 @@ -184,7 +182,7 @@ template bus::status cache_component::write_any (host_int_4 addr, DataType data) { - bus::status st, read_status; + bus::status st, read_status, writeback_status; if (UNLIKELY (downstream == 0)) return bus::unmapped; @@ -237,8 +235,8 @@ cache_component::write_any (host_int_4 a if (expelled_line->valid_p () && expelled_line->dirty_p ()) { // flush a dirty line being replaced - if ((st = write_line (*expelled_line)) != bus::ok) - return st; + if ((writeback_status = write_line (*expelled_line)) != bus::ok) + return writeback_status; } } else @@ -279,7 +277,7 @@ cache_component::write_any (host_int_4 a if (line) st.latency = hit_latency; else - st.latency = read_status.latency + miss_latency; + st.latency = writeback_status.latency + read_status.latency + miss_latency; return st; } @@ -287,7 +285,7 @@ template bus::status cache_component::read_any (host_int_4 addr, DataType& data) { - bus::status st, read_status; + bus::status st, read_status, writeback_status; if (UNLIKELY (downstream == 0)) return bus::unmapped; @@ -327,8 +325,8 @@ cache_component::read_any (host_int_4 ad if (expelled_line->valid_p () && expelled_line->dirty_p ()) { // flush a dirty line being replaced - if ((st = write_line (*expelled_line)) != bus::ok) - return st; + if ((writeback_status = write_line (*expelled_line)) != bus::ok) + return writeback_status; } expelled_line->set_tag (tag); if ((read_status = read_line (*expelled_line)) != bus::ok) @@ -353,7 +351,7 @@ cache_component::read_any (host_int_4 ad if (line) st.latency += hit_latency; else - st.latency = read_status.latency + miss_latency; + st.latency = writeback_status.latency + read_status.latency + miss_latency; return st; } -------------------------------------------------------------------------