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* sid-20110801 Patch to fix cache writeback latency
@ 2011-10-16  7:58 John Wehle
  2011-11-01 14:29 ` John Wehle
  0 siblings, 1 reply; 2+ messages in thread
From: John Wehle @ 2011-10-16  7:58 UTC (permalink / raw)
  To: sid

Currently when the SID cache component replaces a line which is dirty
it writes back the data to memory.  However it ignores that fact that
the writeback adds to the latency causing the simulation to believe
that the replacement of a dirty cache line takes the same amount of
time as the replacement of a clean cache line.

The enclosed patch has been tested on FreeBSD with sid configured for
tomi Borealis (a processor under development by Venray Technology).

ChangeLog:

Sun Oct 16 00:03:43 EDT 2011  John Wehle  (john@feith.com)

	* component/cache/cache.cxx (write_any, read_any): Latency
	should include the writeback of a dirty line.

-- John
------------------------8<------------------------------8<---------------
--- component/cache/cache.cxx.ORIGINAL	2009-04-08 16:39:34.000000000 -0400
+++ component/cache/cache.cxx	2011-10-13 00:22:20.000000000 -0400
@@ -184,7 +182,7 @@ template <typename DataType>
 bus::status
 cache_component::write_any (host_int_4 addr, DataType data)
 {
-  bus::status st, read_status;
+  bus::status st, read_status, writeback_status;
 
   if (UNLIKELY (downstream == 0))
     return bus::unmapped;
@@ -237,8 +235,8 @@ cache_component::write_any (host_int_4 a
 	      if (expelled_line->valid_p () && expelled_line->dirty_p ())
 		{
 		  // flush a dirty line being replaced
-		  if ((st = write_line (*expelled_line)) != bus::ok)
-		    return st;
+		  if ((writeback_status = write_line (*expelled_line)) != bus::ok)
+		    return writeback_status;
 		}
 	    }
 	  else
@@ -279,7 +277,7 @@ cache_component::write_any (host_int_4 a
   if (line)
     st.latency = hit_latency;
   else
-    st.latency = read_status.latency + miss_latency;
+    st.latency = writeback_status.latency + read_status.latency + miss_latency;
   return st;
 }
 
@@ -287,7 +285,7 @@ template <typename DataType>
 bus::status
 cache_component::read_any (host_int_4 addr, DataType& data)
 {
-  bus::status st, read_status;
+  bus::status st, read_status, writeback_status;
 
   if (UNLIKELY (downstream == 0))
     return bus::unmapped;
@@ -327,8 +325,8 @@ cache_component::read_any (host_int_4 ad
 	  if (expelled_line->valid_p () && expelled_line->dirty_p ())
 	    {
 	      // flush a dirty line being replaced
-	      if ((st = write_line (*expelled_line)) != bus::ok)
-		  return st;
+	      if ((writeback_status = write_line (*expelled_line)) != bus::ok)
+		  return writeback_status;
 	    }
 	  expelled_line->set_tag (tag);
 	  if ((read_status = read_line (*expelled_line)) != bus::ok)
@@ -353,7 +351,7 @@ cache_component::read_any (host_int_4 ad
   if (line)
     st.latency += hit_latency;
   else
-    st.latency = read_status.latency + miss_latency;
+    st.latency = writeback_status.latency + read_status.latency + miss_latency;
   return st;
 }
 
-------------------------------------------------------------------------

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