From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12519 invoked by alias); 16 Oct 2011 07:58:27 -0000 Received: (qmail 12357 invoked by uid 22791); 16 Oct 2011 07:58:07 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from feith1.FEITH.COM (HELO feith1.FEITH.COM) (192.251.93.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 16 Oct 2011 05:04:25 +0000 Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.4+Sun/8.12.9) with ESMTP id p9G54N3O021588 for ; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4) with ESMTP id p9G54Nfh025583 for ; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4/Submit) id p9G54N6p025582 for sid@sources.redhat.com; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) Date: Sun, 16 Oct 2011 07:58:00 -0000 From: John Wehle Message-Id: <201110160504.p9G54N6p025582@jwlab.FEITH.COM> To: sid@sources.redhat.com Subject: sid-20110801 Patch to fix multiple cache line aging MIME-Version: 1.0 Content-Type: text/plain X-DCC-dmv.com-Metrics: feith1; whitelist Mailing-List: contact sid-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sourceware.org X-SW-Source: 2011-q4/txt/msg00003.txt.bz2 Currently the SID cache component references the same lru_replacement object each time it creates a lru cache. This causes configurations with multiple caches (e.g. an Icache and Dcache) to use the same lru array to track the line ages which creates problems since the array no longer reflects the age of the lines in either cache. Each cache needs their own (private) lru array. Based on code inspection it appears fifo_replacement suffers the same problem. The enclosed patch has been tested on FreeBSD with sid configured for tomi Borealis (a processor under development by Venray Technology). ChangeLog: Sun Oct 16 00:16:46 EDT 2011 John Wehle (john@feith.com) * component/cache/cache.cxx (CacheCreate): Allocate a new replacement object each time for the fifo and lru types. -- John ------------------------8<------------------------------8<--------------- --- component/cache/cache.cxx.ORIGINAL 2009-04-08 16:39:34.000000000 -0400 +++ component/cache/cache.cxx 2011-10-13 00:22:20.000000000 -0400 @@ -44,8 +44,6 @@ static string replacement_algorithms[] = // One per replacement policy static cache_replacement_null null_replacement; -static cache_replacement_lru lru_replacement; -static cache_replacement_fifo fifo_replacement; static cache_replacement_random random_replacement; static cache_line_factory internal_line_factory; static mep_assoc_replacement_algorithm mep_assoc_replacement; @@ -1335,9 +1341,9 @@ CacheCreate (const string& typeName) return new cache_component (assoc, cache_sz, line_sz, null_replacement, internal_line_factory); if (replace_alg_string == "lru") - return new cache_component (assoc, cache_sz, line_sz, lru_replacement, internal_line_factory); + return new cache_component (assoc, cache_sz, line_sz, *new cache_replacement_lru, internal_line_factory); else if (replace_alg_string == "fifo") - return new cache_component (assoc, cache_sz, line_sz, fifo_replacement, internal_line_factory); + return new cache_component (assoc, cache_sz, line_sz, *new cache_replacement_fifo, internal_line_factory); else if (replace_alg_string == "random") return new cache_component (assoc, cache_sz, line_sz, random_replacement, internal_line_factory); } @@ -1347,9 +1353,9 @@ CacheCreate (const string& typeName) return new blocking_cache_component (assoc, cache_sz, line_sz, null_replacement, internal_line_factory); if (replace_alg_string == "lru") - return new blocking_cache_component (assoc, cache_sz, line_sz, lru_replacement, internal_line_factory); + return new blocking_cache_component (assoc, cache_sz, line_sz, *new cache_replacement_lru, internal_line_factory); else if (replace_alg_string == "fifo") - return new blocking_cache_component (assoc, cache_sz, line_sz, fifo_replacement, internal_line_factory); + return new blocking_cache_component (assoc, cache_sz, line_sz, *new cache_replacement_fifo, internal_line_factory); else if (replace_alg_string == "random") return new blocking_cache_component (assoc, cache_sz, line_sz, random_replacement, internal_line_factory); } ------------------------------------------------------------------------- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16824 invoked by alias); 16 Oct 2011 08:01:22 -0000 Received: (qmail 16815 invoked by uid 22791); 16 Oct 2011 08:01:21 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS X-Spam-Check-By: sourceware.org Received: from feith1.FEITH.COM (HELO feith1.FEITH.COM) (192.251.93.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 16 Oct 2011 08:01:07 +0000 Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.4+Sun/8.12.9) with ESMTP id p9G54N3O021588 for ; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4) with ESMTP id p9G54Nfh025583 for ; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.4+Sun/8.14.4/Submit) id p9G54N6p025582 for sid@sources.redhat.com; Sun, 16 Oct 2011 01:04:23 -0400 (EDT) Date: Thu, 01 Dec 2011 14:29:00 -0000 From: John Wehle Message-ID: <201110160504.p9G54N6p025582@jwlab.FEITH.COM> To: sid@sources.redhat.com Subject: sid-20110801 Patch to fix multiple cache line aging MIME-Version: 1.0 Content-Type: text/plain X-DCC-dmv.com-Metrics: feith1; whitelist Mailing-List: contact sid-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sourceware.org X-SW-Source: 2011-q4/txt/msg00006.txt.bz2 Message-ID: <20111201142900.zFOWlV_dELW020bJWLUnUdfqgfu-J7YjOLFuS72DL8k@z> Currently the SID cache component references the same lru_replacement object each time it creates a lru cache. This causes configurations with multiple caches (e.g. an Icache and Dcache) to use the same lru array to track the line ages which creates problems since the array no longer reflects the age of the lines in either cache. Each cache needs their own (private) lru array. Based on code inspection it appears fifo_replacement suffers the same problem. The enclosed patch has been tested on FreeBSD with sid configured for tomi Borealis (a processor under development by Venray Technology). ChangeLog: Sun Oct 16 00:16:46 EDT 2011 John Wehle (john@feith.com) * component/cache/cache.cxx (CacheCreate): Allocate a new replacement object each time for the fifo and lru types. -- John ------------------------8<------------------------------8<--------------- --- component/cache/cache.cxx.ORIGINAL 2009-04-08 16:39:34.000000000 -0400 +++ component/cache/cache.cxx 2011-10-13 00:22:20.000000000 -0400 @@ -44,8 +44,6 @@ static string replacement_algorithms[] = // One per replacement policy static cache_replacement_null null_replacement; -static cache_replacement_lru lru_replacement; -static cache_replacement_fifo fifo_replacement; static cache_replacement_random random_replacement; static cache_line_factory internal_line_factory; static mep_assoc_replacement_algorithm mep_assoc_replacement; @@ -1335,9 +1341,9 @@ CacheCreate (const string& typeName) return new cache_component (assoc, cache_sz, line_sz, null_replacement, internal_line_factory); if (replace_alg_string == "lru") - return new cache_component (assoc, cache_sz, line_sz, lru_replacement, internal_line_factory); + return new cache_component (assoc, cache_sz, line_sz, *new cache_replacement_lru, internal_line_factory); else if (replace_alg_string == "fifo") - return new cache_component (assoc, cache_sz, line_sz, fifo_replacement, internal_line_factory); + return new cache_component (assoc, cache_sz, line_sz, *new cache_replacement_fifo, internal_line_factory); else if (replace_alg_string == "random") return new cache_component (assoc, cache_sz, line_sz, random_replacement, internal_line_factory); } @@ -1347,9 +1353,9 @@ CacheCreate (const string& typeName) return new blocking_cache_component (assoc, cache_sz, line_sz, null_replacement, internal_line_factory); if (replace_alg_string == "lru") - return new blocking_cache_component (assoc, cache_sz, line_sz, lru_replacement, internal_line_factory); + return new blocking_cache_component (assoc, cache_sz, line_sz, *new cache_replacement_lru, internal_line_factory); else if (replace_alg_string == "fifo") - return new blocking_cache_component (assoc, cache_sz, line_sz, fifo_replacement, internal_line_factory); + return new blocking_cache_component (assoc, cache_sz, line_sz, *new cache_replacement_fifo, internal_line_factory); else if (replace_alg_string == "random") return new blocking_cache_component (assoc, cache_sz, line_sz, random_replacement, internal_line_factory); } -------------------------------------------------------------------------