From: "Frank Ch. Eigler" <fche@redhat.com>
To: Peter Gavin <pgavin@gmail.com>
Cc: cgen@sourceware.org, sid@sourceware.org
Subject: Re: cgen, GNU gdb/sim, and full system simulation
Date: Wed, 16 May 2012 17:07:00 -0000 [thread overview]
Message-ID: <20120516163407.GC32524@redhat.com> (raw)
In-Reply-To: <CAKEMJMqCY3DrU++LRZQMRCFwxndp0EK+4n-ufHMTz7OUGG7aiQ@mail.gmail.com>
Hi -
On Fri, May 11, 2012 at 01:57:11PM +0200, Peter Gavin wrote:
> [...]
> I'm working on a port of the gdb simulator for OpenRISC. I was
> wondering if anyone had any input on how difficult a full-system
> simulator would be to implement vs. the syscall emulated simulators
> the other ports seem to use.
Indeed. For full-system simulators, some projects have used the sid
framework instead of gdb/sim.
> The primary thing I'm concerned about at the moment is virtual
> memory. [...] But it doesn't look like there's a way to translate
> the PC prior to fetching an instruction. [...]
Actually, instruction fetching code can be hand-written in either
gdb-sim (see e.g. sim/m32r/mloop.in extract-*) or sid frameworks
(sid/component/cgen-cpu/m32r/m32rbf.cxx step_insns), and so that code
can map all it likes.
To me, the more interesting question would be the choice to model
virtual memory as a separate component between the CPU and the memory
and I/O buses (which would suite sid's modeling very well), vs
something purely internal to the CPU model. In either case, the
lookup is only one part: page tables, TLBs, page fault events, all
have to be modeled.
- FChE
next parent reply other threads:[~2012-05-16 17:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAKEMJMqCY3DrU++LRZQMRCFwxndp0EK+4n-ufHMTz7OUGG7aiQ@mail.gmail.com>
2012-05-16 17:07 ` Frank Ch. Eigler [this message]
2012-05-18 12:46 ` Peter Gavin
2012-05-18 12:52 ` Frank Ch. Eigler
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