From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18009 invoked by alias); 16 May 2012 17:07:44 -0000 Received: (qmail 17986 invoked by uid 22791); 16 May 2012 17:07:42 -0000 X-SWARE-Spam-Status: No, hits=-5.8 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_DNSWL_HI,SPF_HELO_PASS,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 16 May 2012 17:07:28 +0000 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q4GH7RVo010708 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 16 May 2012 13:07:27 -0400 Received: from fche.csb (vpn-11-135.rdu.redhat.com [10.11.11.135]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q4GH7QkA014528; Wed, 16 May 2012 13:07:26 -0400 Received: by fche.csb (Postfix, from userid 2569) id 21D135813C; Wed, 16 May 2012 12:34:07 -0400 (EDT) Date: Wed, 16 May 2012 17:07:00 -0000 From: "Frank Ch. Eigler" To: Peter Gavin Cc: cgen@sourceware.org, sid@sourceware.org Subject: Re: cgen, GNU gdb/sim, and full system simulation Message-ID: <20120516163407.GC32524@redhat.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.2i X-IsSubscribed: yes Mailing-List: contact sid-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sourceware.org X-SW-Source: 2012-q2/txt/msg00002.txt.bz2 Hi - On Fri, May 11, 2012 at 01:57:11PM +0200, Peter Gavin wrote: > [...] > I'm working on a port of the gdb simulator for OpenRISC. I was > wondering if anyone had any input on how difficult a full-system > simulator would be to implement vs. the syscall emulated simulators > the other ports seem to use. Indeed. For full-system simulators, some projects have used the sid framework instead of gdb/sim. > The primary thing I'm concerned about at the moment is virtual > memory. [...] But it doesn't look like there's a way to translate > the PC prior to fetching an instruction. [...] Actually, instruction fetching code can be hand-written in either gdb-sim (see e.g. sim/m32r/mloop.in extract-*) or sid frameworks (sid/component/cgen-cpu/m32r/m32rbf.cxx step_insns), and so that code can map all it likes. To me, the more interesting question would be the choice to model virtual memory as a separate component between the CPU and the memory and I/O buses (which would suite sid's modeling very well), vs something purely internal to the CPU model. In either case, the lookup is only one part: page tables, TLBs, page fault events, all have to be modeled. - FChE