Hi,

Some sid components don't support misaligned reads/writes. The current 
cache components are the example which caused my particular problem. 
They punt on misaligned reads/writes, presumably so that they don't have 
to worry about accesses which cross cache line boundaries. This causes a 
problem when GDB attempts to read memory at unaligned addresses.

This patch to gdb::process_get_mem and gdb::process_set_mem forces any 
unaligned requests to use the existing byte-at-a-time method.

I've committed this patch. Let me know if there are any problems.

Dave