From: Dave Brolley <brolley@redhat.com>
To: "Frank Ch. Eigler" <fche@redhat.com>
Cc: sid@sources.redhat.com
Subject: Re: Misaligned read/write of memory by GDB
Date: Tue, 29 Jun 2004 20:40:00 -0000 [thread overview]
Message-ID: <40E1D329.1060705@redhat.com> (raw)
In-Reply-To: <20040629191821.GM10148@redhat.com>
Frank Ch. Eigler wrote:
>>I thought about the possibility of fixing existing memory targets to
>>handle misaligned access, either by implementing support, returning
>>sid::bus::misaligned, or whatever else might be appropriate.
>>
>>
>
>How many offenders (that did neither) did you encounter?
>
Just one. The cache component. It silently reads directly from the
backing memory, thus (potentially) returning the wrong value.
>>However it occurred to me that this would require implementors of all
>>future memory targets to be aware of potential GDB access of this
>>type. [...]
>>
>>
>
>True, except that such accesses could originate elsewhere - a simulated
>CPU, or a gloss component, for example.
>
>
I guess one could argue that all complete component implementations
should handle all possible input possibilities. The failure was not
obvious in my case because of the silent misbehavior of the cache
component. I guess I was just wanting to prevent a similar misfortune
from happening to someone else (or me again!) in the future.
Your gloss example convinces me that the cache component should be
fixed, however. Once done, I can implement the GDB access in the way
you've suggested.
Dave
next prev parent reply other threads:[~2004-06-29 20:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-06-28 21:18 Dave Brolley
2004-06-28 22:50 ` Dave Brolley
2004-06-29 18:27 ` Frank Ch. Eigler
2004-06-29 19:14 ` Dave Brolley
2004-06-29 19:18 ` Frank Ch. Eigler
2004-06-29 20:40 ` Dave Brolley [this message]
2004-07-01 17:02 ` Dave Brolley
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