Hello,

About a month ago, Morris Dong asked about modelling bus contention and 
stalls. At that time, I promised that I would submit some work that I 
have done in that area. Apologies for taking so long, but here it is. 
Attached to this message you will find:

o A description of the notion of a blockable component in SID
o An overview of the implementation of the sidutil::blocking_component 
mix-in class
o A description of a blocking cache component implementation
o A description and skeletal example of a blocking cpu implementation
o A description of a new virtual base class: sidutil::bus_arbitrator for 
implementing bus arbitrator components
o A patch which implements all of the above and fixes some bugs I 
noticed while completing the work

This patch has been tested using an internal port which, unfortunately 
can not be submitted at this time. However, it would appear that this 
infrastructure is of interest and possible use to folks like Morris.

As always, comments, suggestions and questions are welcome. I am seeking 
approval to commit this work.

Dave