Hi,

I've committed the attached patch which corrects a long standing problem 
in the sid/sim decoders generated by cgen. These decoders select the 
most commonly fixed bits in the ISA a few at a time until enough bits 
have been selected to uniquely represent one and only one insn from the 
ISA. The problem is that there may still be encodings which match these 
bits but do not represent valid insns. As a result, these invalid 
encodings are simulated as if they were a valid insn.

My first idea was to generate one extra nested switch using the 
remaining opcode bits of the insn which hadn't been used yet. This 
worked, however for some ISAs with only a few insns but lots of opcode 
bits, this can lead to the selection of many more bits for the final 
switch which caused an exponential explosion in the time CGEN takes to 
generate the decoder.

This patch adds one additional test before accepting the insn. Namely, 
it checks that all of the fixed bits in the insn match the ones which 
are begin decoded. This is done by taking the logical 'and' of the 
insn's opcode mask and the bytes being decoded and checking that the 
result is equal to the insn's opcode value.

I've attached a diff of the generated decoder for xstormy16 so that you 
can see the additional tests which are generated.

Let me know if you have any problems or concerns
Dave