* [RFC] New cpu --- Morpho ms1
@ 2005-06-08 20:19 Dave Brolley
2005-06-13 14:55 ` Frank Ch. Eigler
2005-06-14 10:25 ` Nick Clifton
0 siblings, 2 replies; 12+ messages in thread
From: Dave Brolley @ 2005-06-08 20:19 UTC (permalink / raw)
To: cgen; +Cc: sid, binutils
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Hello,
On behalf of Red Hat I would like approval to commit the attached
ms1.cpu and ms1.opc files for CGEN to the src/cpu directory. I will also
be submitting the opcodes and SID ports to their respective lists.
Dave
[-- Attachment #2: ms1.cpu --]
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; Morpho Technologies mRISC CPU description. -*- Scheme -*-
; Copyright (C) 2001 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
(include "simplify.inc")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; define-arch must appear first
(define-arch
(name ms1) ; name of cpu family
(comment "Morpho Technologies mRISC family")
(default-alignment aligned)
(insn-lsb0? #t)
(machs ms1 ms1-003)
(isas ms1)
)
; Instruction set parameters.
(define-isa
(name ms1)
(comment "Morpho Technologies mrisc ISA")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
(parallel-insns 2)
)
\f
; Cpu family definitions.
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
(name ms1bf)
(comment "Morpho Technologies mRISC family")
(endian big)
(word-bitsize 32)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
(name ms1-003bf)
(comment "Morpho Technologies mRISC family")
(endian big)
(word-bitsize 32)
)
(define-mach
(name ms1)
(comment "Morpho Technologies mrisc")
(cpu ms1bf)
(isas ms1)
)
(define-mach
(name ms1-003)
(comment "Morpho Technologies mrisc")
(cpu ms1-003bf)
(isas ms1)
)
\f
; Model descriptions.
; Can probably take the u-exec out. We'll see.
(define-model
(name ms1)
(comment "Morpho Technologies mrisc")
(mach ms1)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-model
(name ms1-003)
(comment "Morpho Technologies mrisc")
(mach ms1-003)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
; Macros to simplify MACH attribute specification.
(define-pmacro MACHMS1 (MACH ms1))
(define-pmacro MACHMS1-003 (MACH ms1-003))
; FIXME: It might simplify things to separate the execute process from the
; one that updates the PC.
\f
;;;;;;;;;;;;;;;;;;;;;;;;
;; Instruction Fields ;;
;;;;;;;;;;;;;;;;;;;;;;;;
; Attributes:
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
; RESERVED: bits are not used to decode insn, must be all 0
; RELOC: there is a relocation associated with this field (experiment)
;
; f-msys: Identify a a morphosys insns. 1 if msys, 0 if not.
; f-opc: 6 bit opcode for non-morphosys instructions.
; f-msopc: 6 bit opcode for morphosys instructions.
; f-imm: flag to indicate use of an immediate operand. 1 if yes, 0 if no.
; f-sr1: source resgister 1. (also used for MSYS insns)
; f-sr2: source register 2. (also used for MSYS insns)
; f-dr: destination register when located in bits 19:16.
; f-drrr: destination register when located in bits 15:12. (also for MSYS insns)
; f-imm16: 16 bit immediate value when not an offset.
; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
; f-uu4a: unused 4 bit field.
; f-uu4b: second unsed 4 bit field.
; f-uu12: unused 12 bit field.
; f-uu16: unused 16 bit field.
; f-uu24: unused 24 bit field.
(dnf f-msys "morphosys insn flag" () 31 1)
(dnf f-opc "opcode field" () 30 6)
(dnf f-imm "immedate flag" () 24 1)
(dnf f-uu24 "unused 24 bits" () 23 24)
(dnf f-sr1 "sr1 register field" (ABS-ADDR) 23 4)
(dnf f-sr2 "sr2 register field" (ABS-ADDR) 19 4)
(dnf f-dr "dr register field" (ABS-ADDR) 19 4)
(dnf f-drrr "drrr register field" (ABS-ADDR) 15 4)
(dnf f-imm16u "unsigned 16 bit immediate" () 15 16)
(df f-imm16s "signed 16 bit immediate" () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0)))
(dnf f-imm16a "pc-rel offset" (PCREL-ADDR) 15 16)
(dnf f-uu4a "unused 4 bit field" () 19 4)
(dnf f-uu4b "unused 4 bit field" () 23 4)
(dnf f-uu12 "unused 12 bit field" () 11 12)
(dnf f-uu16 "unused 16 bit field" () 15 16)
; The following ifields are used exclusively for the MorphoSys instructions.
; In a few cases, a bit field is used for something in addition to what its
; name suggests. For the most part, the names are meaningful though.
(dnf f-msopc "opcode field" () 30 5)
(dnf f-uu-26-25 "unused 26 bits" () 25 26)
(dnf f-mask "mask" () 25 16)
(dnf f-bankaddr "bank address" () 25 13)
(dnf f-rda "rda" () 25 1)
(dnf f-uu-2-25 "unused bits 25 & 24" () 25 2)
(dnf f-rbbc "Omega network configuration" () 25 2)
(dnf f-perm "perm" () 25 2)
(dnf f-mode "mode" () 25 2)
(dnf f-uu-1-24 "testing" () 24 1)
(dnf f-wr "wr" () 24 1)
(dnf f-fbincr "fb incr" () 23 4)
(dnf f-uu-2-23 "unused bits 23 and 22" () 23 2)
(dnf f-xmode "xmode" () 23 1)
(dnf f-a23 "a23" () 23 1)
(dnf f-mask1 "mask1" () 22 3)
(dnf f-cr "cr" () 22 3)
(dnf f-type "type" () 21 2)
(dnf f-incamt "increment amount" () 19 8)
(dnf f-cbs "cbs" () 19 2)
(dnf f-uu-1-19 "unused bit 19" () 19 1)
(dnf f-ball "b_all" () 19 1)
(dnf f-colnum "column number" () 18 3)
(dnf f-brc "b_r_c" () 18 3)
(dnf f-incr "incr" () 17 6)
(dnf f-fbdisp "frame buffer displacement" () 15 6)
(dnf f-uu-4-15 "unused bits 15,14,13,12" () 15 4)
(dnf f-length "length" () 15 3)
(dnf f-uu-1-15 "unused bit 15" () 15 1)
(dnf f-rc "row/column context" () 15 1)
(dnf f-rcnum "starting cell of cntxt mem." () 14 3)
(dnf f-rownum "row number" () 14 3)
(dnf f-cbx "cbx" () 14 3)
(dnf f-id "id" () 14 1)
(dnf f-size "size" () 13 14)
(dnf f-rownum1 "row number" () 12 3)
(dnf f-uu-3-11 "unused 3 bits (11-9)" () 11 3)
(dnf f-rc1 "row/column context" () 11 1)
(dnf f-ccb "ccb" () 11 1)
(dnf f-cbrb "data-bus orientation" () 10 1)
(dnf f-cdb "cdb" () 10 1)
(dnf f-rownum2 "row number" () 9 3)
(dnf f-cell "cell" () 9 3)
(dnf f-uu-3-9 "unused 3 bits (9-7)" () 9 3)
(dnf f-contnum "context number" () 8 9)
(dnf f-uu-1-6 "unused bit 6" () 6 1)
(dnf f-dup "dup" () 6 1)
(dnf f-rc2 "rc2" () 6 1)
(dnf f-ctxdisp "context displacement" () 5 6)
; The following is just for a test
(dnf f-msysfrsr2 "sr2 for msys" () 19 4)
(dnf f-brc2 "b_r_c2" () 14 3)
(dnf f-ball2 "b_all2" () 15 1)
\f
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Enumerations Of Instruction Fields ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; insn-msys: bit 31. 1 for Morphosys Insns, 0 if not.
(define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys
(NO YES)
)
; insn-opc: bits 30 through 25 . Non-MorphoSys Instructions
; Note - the documentation is wrong for the encoding of the DBNZ
; instruction. It is actually 011110. See Issue 67699.
(define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc
(ADD ADDU SUB SUBU MUL - - -
AND OR XOR NAND NOR XNOR LDUI -
LSL LSR ASR - - - - -
BRLT BRLE BREQ JMP JAL BRNEQ DBNZ -
LDW STW - - - - - -
- - - - - - - -
EI DI SI RETI BREAK IFLUSH - -
)
)
; insn-msopc: bits 30 through 26 . MorphoSys Instructions
(define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc
(LDCTXT LDFB STFB FBCB MFBCB FBCCI FBRCI FBCRI
FBRRI MFBCCI MFBRCI MFBCRI MFBRRI FBCBDR RCFBCB MRCFBCB
CBCAST DUPCBCAST WFBI WFB RCRISC FBCBINC RCXMODE INTLVR
WFBINC MWFBINC WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS
- - - - - - - -
)
)
; insn-imm: bit 24. Immediate operand indicator.
(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm
; This bit specifies whether and immediate operand will be present.
; It's 1 if ther is, 0 if there is not.
(NO YES)
)
;;;;;;;;;;;;;;;;
;; Attributes ;;
;;;;;;;;;;;;;;;;
; Might not need this. Keep if for the sim just in case.
;(define-attr
; (for insn)
; (type boolean)
; (name EXT-SKIP-INSN)
; (comment "instruction is a PAGE, LOADL or LOADH instruction")
;)
(define-attr
(for insn)
(type boolean)
(name LOAD-DELAY)
(comment "insn has a load delay")
)
(define-attr
(for insn)
(type boolean)
(name MEMORY-ACCESS)
(comment "insn performs a memory access")
)
(define-attr
(for insn)
(type boolean)
(name AL-INSN)
(comment "insn is an arithmetic or logic insn.")
)
(define-attr
(for insn)
(type boolean)
(name IO-INSN)
(comment "insn performs an I/O operation")
)
(define-attr
(for insn)
(type boolean)
(name BR-INSN)
(comment "insn performs an I/O operation")
)
(define-pmacro (define-reg-use-attr regfield)
(define-attr
(for insn)
(type boolean)
(name (.sym "USES-" (.upcase regfield)))
(comment ("insn accesses register operand " regfield))))
(define-reg-use-attr "frdr")
(define-reg-use-attr "frdrrr")
(define-reg-use-attr "frsr1")
(define-reg-use-attr "frsr2")
; Might not need this. Keep it for the sim just in case.
(define-attr
(for insn)
(type boolean)
(name SKIPA)
(comment "instruction is a SKIP instruction")
)
;;;;;;;;;;;;;;;;;;;;;
;; Hardware Pieces ;;
;;;;;;;;;;;;;;;;;;;;;
;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n))
; These are the 16 registers that the chip has. In later versions
; where there will be more registers, this will need to be expanded.
; Note that there are two entries for the registers with two names.
(define-hardware
(name h-spr)
(comment "special-purpose registers")
(type register SI (16))
(indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5)
("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12)
("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15)))
; (get (index) (and (raw-reg h-spr) #xffffffff))
; (set (index value) (set (raw-reg h-spr) (and value #xffffffff)))
)
; This is the program counter.
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
(define-keyword
(name msys-syms)
(print-name h-nil)
(prefix "")
(values (DUP 1) (XX 0))
)
;;;;;;;;;;;;;;
;; Operands ;;
;;;;;;;;;;;;;;
(define-operand (name frsr1) (comment "register") (attrs)
(type h-spr) (index f-sr1) )
(define-operand (name frsr2) (comment "register") (attrs)
(type h-spr) (index f-sr2) )
(define-operand (name frdr) (comment "register") (attrs)
(type h-spr) (index f-dr) )
(define-operand (name frdrrr) (comment "register") (attrs)
(type h-spr) (index f-drrr) )
(define-operand (name imm16) (comment "immediate value - sign extd") (attrs)
(type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs)
(type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))
(define-operand (name imm16o) (comment "immediate value") (attrs)
(type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
; Operands for MorphoSys Instructions
(define-operand (name rc) (comment "rc") (attrs)
(type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex")))
(define-operand (name rcnum) (comment "rcnum") (attrs)
(type h-uint) (index f-rcnum) (handlers (print "dollarhex")))
(define-operand (name contnum) (comment "context number") (attrs)
(type h-uint) (index f-contnum) (handlers (print "dollarhex")))
(define-operand (name rbbc) (comment "omega network configuration") (attrs)
(type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex")))
(define-operand (name colnum) (comment "column number") (attrs)
(type h-uint) (index f-colnum) (handlers (print "dollarhex")))
(define-operand (name rownum) (comment "row number") (attrs)
(type h-uint) (index f-rownum) (handlers (print "dollarhex")))
(define-operand (name rownum1) (comment "row number") (attrs)
(type h-uint) (index f-rownum1) (handlers (print "dollarhex")))
(define-operand (name rownum2) (comment "row number") (attrs)
(type h-uint) (index f-rownum2) (handlers (print "dollarhex")))
(define-operand (name rc1) (comment "rc1") (attrs)
(type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex")))
(define-operand (name rc2) (comment "rc2") (attrs)
(type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex")))
(define-operand (name cbrb) (comment "data-bus orientation") (attrs)
(type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex")))
(define-operand (name cell) (comment "cell") (attrs)
(type h-uint) (index f-cell) (handlers (print "dollarhex")))
(define-operand (name dup) (comment "dup") (attrs)
(type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex")))
(define-operand (name ctxdisp) (comment "context displacement") (attrs)
(type h-uint) (index f-ctxdisp) (handlers (print "dollarhex")))
(define-operand (name fbdisp) (comment "frame buffer displacement") (attrs)
(type h-uint) (index f-fbdisp) (handlers (print "dollarhex")))
(define-operand (name type) (comment "type") (attrs)
(type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex")))
(define-operand (name mask) (comment "mask") (attrs)
(type h-uint) (index f-mask) (handlers (print "dollarhex")))
(define-operand (name bankaddr) (comment "bank address") (attrs)
(type h-uint) (index f-bankaddr) (handlers (print "dollarhex")))
(define-operand (name incamt) (comment "increment amount") (attrs)
(type h-uint) (index f-incamt) (handlers (print "dollarhex")))
(define-operand (name xmode) (comment "xmode") (attrs)
(type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex")))
(define-operand (name mask1) (comment "mask1") (attrs)
(type h-uint) (index f-mask1) (handlers (print "dollarhex")))
(define-operand (name ball) (comment "b_all") (attrs)
(type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex")))
(define-operand (name brc) (comment "b_r_c") (attrs)
(type h-uint) (index f-brc) (handlers (print "dollarhex")))
(define-operand (name rda) (comment "rd") (attrs)
(type h-uint) (index f-rda) (handlers (print "dollarhex")))
(define-operand (name wr) (comment "wr") (attrs)
(type h-uint) (index f-wr) (handlers (print "dollarhex")))
(define-operand (name ball2) (comment "b_all2") (attrs)
(type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex")))
(define-operand (name brc2) (comment "b_r_c2") (attrs)
(type h-uint) (index f-brc2) (handlers (print "dollarhex")))
(define-operand (name perm) (comment "perm") (attrs)
(type h-uint) (index f-perm) (handlers (print "dollarhex")))
(define-operand (name a23) (comment "a23") (attrs)
(type h-uint) (index f-a23) (handlers (print "dollarhex")))
(define-operand (name cr) (comment "c-r") (attrs)
(type h-uint) (index f-cr) (handlers (print "dollarhex")))
(define-operand (name cbs) (comment "cbs") (attrs)
(type h-uint) (index f-cbs) (handlers (print "dollarhex")))
(define-operand (name incr) (comment "incr") (attrs)
(type h-uint) (index f-incr) (handlers (print "dollarhex")))
(define-operand (name length) (comment "length") (attrs)
(type h-uint) (index f-length) (handlers (print "dollarhex")))
(define-operand (name cbx) (comment "cbx") (attrs)
(type h-uint) (index f-cbx) (handlers (print "dollarhex")))
(define-operand (name ccb) (comment "ccb") (attrs)
(type h-uint) (index f-ccb) (handlers (print "dollarhex")))
(define-operand (name cdb) (comment "cdb") (attrs)
(type h-uint) (index f-cdb) (handlers (print "dollarhex")))
; For the INTLVR insn
(define-operand (name mode) (comment "mode") (attrs)
(type h-uint) (index f-mode) (handlers (print "dollarhex")))
(define-operand (name id) (comment "i/d") (attrs)
(type h-uint) (index f-id) (handlers (print "dollarhex")))
(define-operand (name size) (comment "size") (attrs)
(type h-uint) (index f-size) (handlers (print "dollarhex")))
(define-operand (name fbincr) (comment "fb incr") (attrs)
(type h-uint) (index f-fbincr) (handlers (print "dollarhex")))
; Probaby won't need most of these.
(define-pmacro r0 (reg h-spr #x0))
(define-pmacro r1 (reg h-spr #x01))
(define-pmacro r2 (reg h-spr #x02))
(define-pmacro r3 (reg h-spr #x03))
(define-pmacro r4 (reg h-spr #x04))
(define-pmacro r5 (reg h-spr #x05))
(define-pmacro r6 (reg h-spr #x06))
(define-pmacro r7 (reg h-spr #x07))
(define-pmacro r8 (reg h-spr #x08))
(define-pmacro r9 (reg h-spr #x09))
(define-pmacro r10 (reg h-spr #xA))
(define-pmacro r11 (reg h-spr #xB))
(define-pmacro r12 (reg h-spr #xC))
(define-pmacro fp (reg h-spr #xC))
(define-pmacro r13 (reg h-spr #xD))
(define-pmacro sp (reg h-spr #xD))
(define-pmacro r14 (reg h-spr #xE))
(define-pmacro ra (reg h-spr #xE))
(define-pmacro r15 (reg h-spr #xF))
(define-pmacro ira (reg h-spr #xF))
; delayed set
(define-pmacro (dset dest src) (set (delay 1 dest) src))
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Instructions As Defined In the MorphoRisc ISA Document ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Arithmetic Instructions
(dni add "ADD DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"add $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (add SI frsr1 frsr2))
()
)
(dni addu "ADDU DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"addu $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (add USI frsr1 frsr2))
()
)
(dni addi "ADDI DstReg, SrcReg1 UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"addi $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16)
(sequence((HI tmp))
(set HI tmp (and imm16 #xffff))
(set frdr (add SI frsr1 (ext SI tmp)))
)
()
)
(dni addui "ADDUI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"addui $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z)
(set frdr (add USI frsr1 (ext USI imm16z)))
()
)
(dni sub "SUB DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"sub $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (sub SI frsr1 frsr2))
()
)
(dni subu "SUBU DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"subu $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (sub USI frsr1 frsr2))
()
)
(dni subi "SUBI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"subi $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16)
(sequence((HI tmp))
(set HI tmp (and imm16 #xffff))
(set frdr (sub SI frsr1 (ext SI tmp)))
)
;(set frdr (sub SI frsr1 (ext SI imm16)))
()
)
(dni subui "SUBUI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"subui $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z)
(set frdr (sub USI frsr1 (ext USI imm16z)))
()
)
(dni mul "MUL DstReg, SrcReg1, SrcReg2"
(MACHMS1-003 AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"mul $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(sequence((HI op1) (HI op2))
(set op1 (and frsr1 #xffff))
(if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
(error "operand out of range")
)
(set op2 (and frsr2 #xffff))
(if (or (lt op2 (const -32768)) (gt op2 (const 32767)))
(error "operand out of range")
)
(set frdrrr (mul SI (ext SI op1) (ext SI op2)))
)
()
)
(dni muli "MULI DstReg, SrcReg1, UnsImm"
(MACHMS1-003 AL-INSN USES-FRDR USES-FRSR1)
"muli $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16)
(sequence((HI op1) (HI op2))
(set op1 (and frsr1 #xffff))
(if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
(error "operand out of range")
)
(set op2 (and imm16 #xffff))
(if (eq op1 (const 0))
(error "op1 is 0")
)
(if (eq op2 (const 0))
(error "op2 is 0")
)
(set frdr (mul SI (ext SI op1) (ext SI op2)))
)
()
)
; Logical Instructions
(dni and "AND DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"and $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (and frsr1 frsr2))
()
)
(dni andi "ANDI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"andi $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z)
(set frdr (and frsr1 (ext USI imm16z)))
()
)
(dni or "OR DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"or $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (or frsr1 frsr2))
()
)
(dni nop "nop"
()
"nop"
(+ MSYS_NO OPC_OR IMM_NO (f-uu24 0))
(nop)
()
)
(dni ori "ORI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"ori $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z)
(set frdr (or frsr1 (ext USI imm16z)))
()
)
(dni xor "XOR DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"xor $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (xor frsr1 frsr2))
()
)
(dni xori "XORI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"xori $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z)
(set frdr (xor frsr1 (ext USI imm16z)))
()
)
(dni nand "NAND DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"nand $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (inv (and frsr1 frsr2)))
()
)
(dni nandi "NANDI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"nandi $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z)
(set frdr (inv (and frsr1 (ext USI imm16z))))
()
)
(dni nor "NOR DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"nor $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (inv (or frsr1 frsr2)))
()
)
(dni nori "NORI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"nori $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z)
(set frdr (inv (or frsr1 (ext USI imm16z))))
()
)
(dni xnor "XNOR DstReg, SrcReg1, SrcReg2"
(AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
"xnor $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (inv (xor frsr1 frsr2)))
()
)
(dni xnori "XNORI DstReg, SrcReg1, UnsImm"
(AL-INSN USES-FRDR USES-FRSR1)
"xnori $frdr,$frsr1,#$imm16z"
(+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z)
(set frdr (inv (xor frsr1 (ext USI imm16z))))
()
)
(dni ldui "LDUI DstReg, UnsImm"
(AL-INSN USES-FRDR)
"ldui $frdr,#$imm16z"
(+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z)
(set frdr (and (sll imm16z 16) #xffff0000))
()
)
; Shift Instructions
(dni lsl "LSL DstReg, SrcReg1, SrcReg2"
(USES-FRDRRR USES-FRSR1 USES-FRSR2)
"lsl $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (sll frsr1 frsr2))
()
)
(dni lsli "LSLI DstReg, SrcReg1, UnsImm"
(USES-FRDR USES-FRSR1)
"lsli $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16)
(set frdr (sll frsr1 imm16))
()
)
(dni lsr "LSR DstReg, SrcReg1, SrcReg2"
(USES-FRDRRR USES-FRSR1 USES-FRSR2)
"lsr $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (srl frsr1 frsr2))
()
)
(dni lsri "LSRI DstReg, SrcReg1, UnsImm"
(USES-FRDR USES-FRSR1)
"lsri $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16)
(set frdr (srl frsr1 imm16))
()
)
(dni asr "ASR DstReg, SrcReg1, SrcReg2"
(USES-FRDRRR USES-FRSR1 USES-FRSR2)
"asr $frdrrr,$frsr1,$frsr2"
(+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
(set frdrrr (sra frsr1 frsr2))
()
)
(dni asri "ASRI DstReg, SrcReg1, UnsImm"
(USES-FRDR USES-FRSR1)
"asri $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16)
(set frdr (sra frsr1 imm16))
()
)
; Control Transfer Instructions
(dni brlt "BRLT SrcReg1, SrcReg2, label"
(BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2)
"brlt $frsr1,$frsr2,$imm16o"
(+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o)
(sequence()
(if (lt USI frsr1 frsr2)
(dset pc (add pc (ext SI imm16o))))
)
()
)
(dni brle "BRLE SrcReg1, SrcReg2, label"
(BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
"brle $frsr1,$frsr2,$imm16o"
(+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o)
(sequence()
(if (le USI frsr1 frsr2)
(dset pc (add pc (ext SI imm16o))))
)
()
)
(dni breq "BREQ SrcReg1, SrcReg2, label"
(BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
"breq $frsr1,$frsr2,$imm16o"
(+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o)
(sequence()
(if (eq USI frsr1 frsr2)
(dset pc (add pc (ext SI imm16o))))
)
()
)
(dni brne "BRNE SrcReg1, SrcReg2, label"
(BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
"brne $frsr1,$frsr2,$imm16o"
(+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o)
(sequence()
(if (not (eq USI frsr1 frsr2))
(dset pc (add pc (ext SI imm16o))))
)
()
)
(dni jmp "JMP, label"
(DELAY-SLOT BR-INSN)
"jmp $imm16o"
(+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o)
(dset pc (add pc (ext SI imm16o)))
()
)
(dni jal "JAL DstReg, SrcReg1"
(BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1)
"jal $frdrrr,$frsr1"
(+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0))
(sequence()
(if (eq frsr1 #x0)
(c-call VOID "do_syscall" pc)
(sequence() ; else part. Do non-syscall stuff here.
(dset frdrrr (add pc #x8))
(dset pc frsr1)
)
)
)
()
)
(dni dbnz "DBNZ SrcReg1, label"
(MACHMS1-003 BR-INSN DELAY-SLOT USES-FRSR1)
"dbnz $frsr1,$imm16o"
(+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o)
(sequence()
(if (not (eq USI frsr1 0))
(dset pc (add pc (ext SI imm16o))))
)
()
)
; Interrupt Control Instructions
(dni ei "EI - Enable Interrupt Processing"
()
"ei"
(+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
(c-call VOID "enable_interrupts")
()
)
(dni di "DI - Disable Interrupt Processing"
()
"di"
(+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
(c-call VOID "disable_interrupts")
()
)
(dni si "SI - Send software Interrupt"
(DELAY-SLOT BR-INSN USES-FRDR)
"si $frdrrr"
(+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0))
;(sequence()
; (dset frdr (add pc #x4))
; (c-call VOID "do_syscall1" pc)
; ; (dset pc frsr1) Do this later when we have the address.
;)
(sequence()
(set frdrrr (add pc #x4))
(c-call VOID "do_syscall" pc)
; (set pc frsr1) Do this later when we have the address.
)
()
)
(dni reti "RETI SrcReg1"
(DELAY-SLOT BR-INSN USES-FRSR1)
"reti $frsr1"
(+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0))
(sequence()
(c-call VOID "enable_interrupts")
(dset pc frsr1)
)
()
)
; Memory Access Instructions
(dni ldw "LDW DstReg, SrcReg1, Imm"
(LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1)
"ldw $frdr,$frsr1,#$imm16"
(+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16)
(sequence((USI ea) (HI tmp))
(set HI tmp (and imm16 #xffff))
(set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
(set frdr (mem SI ea))
)
()
)
(dni stw "STW SrcReg2, SrcReg1, Imm"
(MEMORY-ACCESS USES-FRSR1 USES-FRSR2)
"stw $frsr2,$frsr1,#$imm16"
(+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16)
(sequence((USI ea) (HI tmp))
(set HI tmp (and imm16 #xffff))
(set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
(set (mem SI ea) frsr2)
)
()
)
; Break Instruction
(dni break "BREAK"
()
"break"
(+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0))
(c-call VOID "do_break" pc)
()
)
; Cache Flush Instruction
(dni iflush "IFLUSH"
(MACHMS1-003)
"iflush"
(+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0))
(nop)
()
)
; MorphoSys Instructions
(dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#"
()
"ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum"
(+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0)
contnum )
(nop)
()
)
(dni ldfb "LDFB SRC1, byte#"
()
"ldfb $frsr1,$frsr2,#$imm16z"
(+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
(nop)
()
)
(dni stfb "STFB SRC1, SRC2, byte "
()
"stfb $frsr1,$frsr2,#$imm16z"
(+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
(nop)
()
)
(dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
()
"fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp)
(nop)
()
)
(dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp"
()
"mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
()
"fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
(nop)
()
)
(dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
()
"fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
(nop)
()
)
(dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
()
"fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
(nop)
()
)
(dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
()
"fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
(nop)
()
)
(dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
()
"mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
(nop)
()
)
(dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
()
"mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
(nop)
()
)
(dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
()
"mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
(nop)
()
)
(dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
()
"mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
(nop)
()
)
(dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
()
"fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp"
()
"rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp"
()
"mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni cbcast "CBCAST mask, r/c, ctx_disp "
()
"cbcast #$mask,#$rc2,#$ctxdisp"
(+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp)
(nop)
()
)
(dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp "
()
"dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp"
(+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp)
(nop)
()
)
(dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp "
()
"wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp)
(nop)
()
)
;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp"
; ()
; "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp"
; (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp)
; (nop)
; ()
;)
(dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp"
()
"wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp"
(+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp)
(nop)
()
)
(dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp"
()
"rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp "
()
"fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp)
(nop)
()
)
(dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp"
()
"rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp"
(+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp)
(nop)
()
)
(dni interleaver "INTLVR ireg, mode, ireg, i/d, size"
()
"intlvr $frsr1,#$mode,$frsr2,#$id,#$size"
(+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size)
(nop)
()
)
;; Issue 66262: The documenatation gives the wrong order for
;; the arguments to the WFBINC instruction.
(dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
(MACHMS1-003)
"wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp)
(nop)
()
)
(dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp"
(MACHMS1-003)
"mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp)
(nop)
()
)
(dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp"
(MACHMS1-003)
"wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp)
(nop)
()
)
(dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp"
(MACHMS1-003)
"mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp)
(nop)
()
)
(dni fbcbincs "FBCBINCS perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
(MACHMS1-003)
"fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp)
(nop)
()
)
(dni mfbcbincs "MFBCBINCS ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
(MACHMS1-003)
"mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp)
(nop)
()
)
(dni fbcbincrs "FBCBINCRS ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
(MACHMS1-003)
"fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
(nop)
()
)
(dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
(MACHMS1-003)
"mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
(+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
(nop)
()
)
[-- Attachment #3: ms1.opc --]
[-- Type: text/plain, Size: 10403 bytes --]
/* MS1 opcode support. -*- C -*-
Copyright (C) 2001, 2002, 2005 Red Hat, Inc.
This file is part of CGEN. */
/*
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h"
*/
\f
/* -- opc.h */
/* Check applicability of instructions against machines. */
#define CGEN_VALIDATE_INSN_SUPPORTED
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
/* Override disassembly hashing - there are variable bits in the top
byte of these instructions. */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
#define CGEN_ASM_HASH_SIZE 127
#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn)
extern unsigned int ms1_asm_hash (const char *);
extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
\f
/* -- opc.c */
#include "safe-ctype.h"
/* Special check to ensure that instruction exists for given machine. */
int
ms1_cgen_insn_supported (CGEN_CPU_DESC cd,
const CGEN_INSN *insn)
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
/* No mach attribute? Assume it's supported for all machs. */
if (machs == 0)
return 1;
return ((machs & cd->machs) != 0);
}
/* A better hash function for instruction mnemonics. */
unsigned int
ms1_asm_hash (const char* insn)
{
unsigned int hash;
const char* m = insn;
for (hash = 0; *m && ! ISSPACE (*m); m++)
hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
/* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
return hash % CGEN_ASM_HASH_SIZE;
}
\f
/* -- asm.c */
static int signed_out_of_bounds (long);
static const char * parse_imm16 (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_dup (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_ball (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_xmode (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_rc (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_cbrb (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_rbbc (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_type (CGEN_CPU_DESC, const char **, int, long *);
/* Range checking for signed numbers. Returns 0 if acceptable
and 1 if the value is out of bounds for a signed quantity. */
static int
signed_out_of_bounds (long val)
{
if ((val < -32768) || (val > 32767))
return 1;
return 0;
}
static const char *
parse_imm16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
bfd_vma value;
/* Is it a control transfer instructions? */
if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O)
{
code = BFD_RELOC_16_PCREL;
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
if (signed_out_of_bounds (value))
errmsg = _("Operand out of range. Must be between -32768 and 32767.");
}
*valuep = value;
return errmsg;
}
/* If it's not a control transfer instruction, then
we have to check for %OP relocating operators. */
if (strncmp (*strp, "%hi16", 5) == 0)
{
*strp += 5;
code = BFD_RELOC_HI16;
}
else if (strncmp (*strp, "%lo16", 5) == 0)
{
*strp += 5;
code = BFD_RELOC_LO16;
}
/* If we found a %OP relocating operator, then parse it as an address.
If not, we need to parse it as an integer, either signed or unsigned
depending on which operand type we have. */
if (code != BFD_RELOC_NONE)
{
/* %OP relocating operator found. */
errmsg = cgen_parse_address (cd, strp, opindex, code,
& result_type, & value);
if (errmsg == NULL)
{
switch (result_type)
{
case (CGEN_PARSE_OPERAND_RESULT_NUMBER):
if (code == BFD_RELOC_HI16)
value = (value >> 16) & 0xFFFF;
else if (code == BFD_RELOC_LO16)
value = value & 0xFFFF;
else
errmsg = _("Biiiig Trouble in parse_imm16!");
break;
case (CGEN_PARSE_OPERAND_RESULT_QUEUED):
/* No special processing for this case. */
break;
default:
errmsg = _("%operator operand is not a symbol");
break;
}
}
*valuep = value;
}
else
{
/* Parse hex values like 0xffff as unsigned, and sign extend
them manually. */
int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16);
if ((*strp)[0] == '0'
&& ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
parse_signed = 0;
/* No relocating operator. Parse as an number. */
if (parse_signed)
{
/* Parse as as signed integer. */
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
if (errmsg == NULL)
{
#if 0
/* Manual range checking is needed for the signed case. */
if (*valuep & 0x8000)
value = 0xffff0000 | *valuep;
else
value = *valuep;
if (signed_out_of_bounds (value))
errmsg = _("Operand out of range. Must be between -32768 and 32767.");
/* Truncate to 16 bits. This is necessary
because cgen will have sign extended *valuep. */
*valuep &= 0xFFFF;
#endif
}
}
else
{
/* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
if (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16
&& *valuep >= 0x8000
&& *valuep <= 0xffff)
*valuep -= 0x10000;
}
}
return errmsg;
}
static const char *
parse_dup (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0)
{
*strp += 3;
*valuep = 1;
}
else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0)
{
*strp += 2;
*valuep = 0;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_ball (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0)
{
*strp += 3;
*valuep = 1;
}
else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0)
{
*strp += 3;
*valuep = 0;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_xmode (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0)
{
*strp += 2;
*valuep = 1;
}
else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0)
{
*strp += 2;
*valuep = 0;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_rc (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0)
{
*strp += 1;
*valuep = 1;
}
else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0)
{
*strp += 1;
*valuep = 0;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_cbrb (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0)
{
*strp += 2;
*valuep = 1;
}
else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0)
{
*strp += 2;
*valuep = 0;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_rbbc (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0)
{
*strp += 2;
*valuep = 0;
}
else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0)
{
*strp += 3;
*valuep = 1;
}
else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0)
{
*strp += 3;
*valuep = 2;
}
else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0)
{
*strp += 2;
*valuep = 3;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
return errmsg;
}
static const char *
parse_type (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg = NULL;
if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0)
{
*strp += 3;
*valuep = 0;
}
else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0)
{
*strp += 4;
*valuep = 1;
}
else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0)
{
*strp += 2;
*valuep = 2;
}
else
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
if ((errmsg == NULL) && (*valuep == 3))
errmsg = _("invalid operand. type may have values 0,1,2 only.");
return errmsg;
}
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
static void
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "$%x", value);
if (0)
print_normal (cd, dis_info, value, attrs, pc, length);
}
/* -- */
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-08 20:19 [RFC] New cpu --- Morpho ms1 Dave Brolley
@ 2005-06-13 14:55 ` Frank Ch. Eigler
2005-06-15 21:37 ` Dave Brolley
2005-06-15 21:39 ` Dave Brolley
2005-06-14 10:25 ` Nick Clifton
1 sibling, 2 replies; 12+ messages in thread
From: Frank Ch. Eigler @ 2005-06-13 14:55 UTC (permalink / raw)
To: Dave Brolley; +Cc: cgen, sid, binutils
[-- Attachment #1: Type: text/plain, Size: 543 bytes --]
Hi -
On Wed, Jun 08, 2005 at 04:18:58PM -0400, Dave Brolley wrote:
> [...]
> On behalf of Red Hat I would like approval to commit the attached
> ms1.cpu and ms1.opc files for CGEN to the src/cpu directory.
From what I gather, src/cpu contains FSF-reassigned files. If the
intent is to donate ms1.* in this way, go ahead. If not, then they
are welcome under cgen/cpu.
> I will also be submitting the opcodes and SID ports to their
> respective lists.
With respect to cgen/sid-bound sources, commit at will.
- FChE
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-08 20:19 [RFC] New cpu --- Morpho ms1 Dave Brolley
2005-06-13 14:55 ` Frank Ch. Eigler
@ 2005-06-14 10:25 ` Nick Clifton
2005-06-15 15:40 ` Dave Brolley
1 sibling, 1 reply; 12+ messages in thread
From: Nick Clifton @ 2005-06-14 10:25 UTC (permalink / raw)
To: Dave Brolley; +Cc: cgen, sid, binutils
Hi Dave,
These files are approved for contribution into the
<binutils>/cgen/cpu directory.
Of course we would prefer it if the copyright on these files was
assigned to the FSF and then they could be contributed to the
<binutils>/cpu directory. Perhaps you could ask RedHat management if
this could be done ?
Cheers
Nick
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-14 10:25 ` Nick Clifton
@ 2005-06-15 15:40 ` Dave Brolley
0 siblings, 0 replies; 12+ messages in thread
From: Dave Brolley @ 2005-06-15 15:40 UTC (permalink / raw)
To: Nick Clifton; +Cc: cgen, sid, binutils
Nick Clifton wrote:
> Hi Dave,
>
> These files are approved for contribution into the
> <binutils>/cgen/cpu directory.
>
> Of course we would prefer it if the copyright on these files was
> assigned to the FSF and then they could be contributed to the
> <binutils>/cpu directory. Perhaps you could ask RedHat management if
> this could be done ?
>
Yes, this was the intent. I have changed the copyrights of both files
using the copyrights from the frv files as a template and have committed
these files to the <binutils>/cpu directory.
Dave
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-13 14:55 ` Frank Ch. Eigler
@ 2005-06-15 21:37 ` Dave Brolley
2005-06-15 21:46 ` Doug Evans
2005-06-15 21:39 ` Dave Brolley
1 sibling, 1 reply; 12+ messages in thread
From: Dave Brolley @ 2005-06-15 21:37 UTC (permalink / raw)
To: cgen; +Cc: sid
[-- Attachment #1: Type: text/plain, Size: 850 bytes --]
Frank Ch. Eigler wrote:
>>I will also be submitting the opcodes and SID ports to their
>>respective lists.
>>
>>
>
>With respect to cgen/sid-bound sources, commit at will.
>
>
>
I've committed, on behalf of Red Hat and the original author, Graydon
Hoare, the attached patch which implements, for SID only, an
implementation of delayed read/writes which is useful for implementing
cpus with exposed pipelines, delay slots and parallel execution. I
think the user level description which has been added cgen/doc/rtl.texi
describes the new functionality pretty well.
There is no effect on existing SID ports or opcodes. This new
functionaility has been used in the implementation of the Morpho ms1
(patch on the way).
This patch also adds the automatic generation of streaming methods for cgen hardware to each cpu.
Regards,
Dave
Dave
[-- Attachment #2: cgen.sid-par.patch.ChangeLog --]
[-- Type: text/plain, Size: 1487 bytes --]
2005-06-15 Dave Brolley <brolley@redhat.com>
* sid-cpu.scm (-gen-hw-stream-and-destream-fns): New function.
(cgen-cpu.h): Call it.
Contributed on behalf of Graydon Hoare
2001-06-05 graydon hoare <graydon@redhat.com>
* utils.scm (foldl): Define.
(foldr): Define.
(filter): Define.
(union): Define.
(intersection): Simplify.
* sid.scm : Set APPLICATION to SID-SIMULATOR.
(-op-gen-delayed-set-maybe-trace): Define.
(<operand> 'gen-set-{quiet,trace}): Delegate to
op-gen-delayed-set-quiet etc. Note: this is still a little tangled
up and needs cleaning.
(-with-parallel?): Hardwire with-parallel to #t.
(<operand> 'cxmake-get): Replace with lookahead-aware code
* sid-decode.scm: Remove per-insn writeback fns.
(-gen-idesc-decls): Redefine sem_fn type.
* sid-cpu.scm (gen-write-stack-structure): Replace parexec stuff
with write stack stuff.
(cgen-write.cxx): Replace per-insn writebacks with single write
stack writeback. Add write stack reset function.
(-gen-scache-semantic-fn insn): Replace parexec stuff with write
stack stuff.
* rtl-c.scm (xop): Clone operand into delayed operand if #:delayed
estate attribute set.
(delay): Set #:delayed attribute to calculated delay, update
maximum delay of cpu, check (delay ...) usage.
* operand.scm (<operand>): Add delayed slot to <operand>.
* mach.scm (<cpu>): Add max-delay slot to <cpu>.
* dev.scm (load-sid): Set APPLICATION to SID-SIMULATOR.
* doc/rtl.texi (Expressions): Add section on (delay ...).
[-- Attachment #3: cgen.sid-par.patch.txt --]
[-- Type: text/plain, Size: 47044 bytes --]
Index: cgen/dev.scm
===================================================================
RCS file: /cvs/src/src/cgen/dev.scm,v
retrieving revision 1.8
diff -c -p -r1.8 dev.scm
*** cgen/dev.scm 15 Feb 2005 09:01:35 -0000 1.8
--- cgen/dev.scm 15 Jun 2005 20:58:25 -0000
***************
*** 132,138 ****
(load "sid-model")
(load "sid-decode")
(set! verbose-level 3)
! (set! APPLICATION 'SIMULATOR)
)
(define (load-sim)
--- 132,138 ----
(load "sid-model")
(load "sid-decode")
(set! verbose-level 3)
! (set! APPLICATION 'SID-SIMULATOR)
)
(define (load-sim)
Index: cgen/mach.scm
===================================================================
RCS file: /cvs/src/src/cgen/mach.scm,v
retrieving revision 1.8
diff -c -p -r1.8 mach.scm
*** cgen/mach.scm 9 Oct 2003 20:49:24 -0000 1.8
--- cgen/mach.scm 15 Jun 2005 20:58:25 -0000
***************
*** 1155,1167 ****
; Allow a cpu family to override the isa parallel-insns spec.
; ??? Concession to the m32r port which can go away, in time.
parallel-insns
)
nil)
)
; Accessors.
! (define-getters <cpu> cpu (word-bitsize insn-chunk-bitsize file-transform parallel-insns))
; Return endianness of instructions.
--- 1155,1173 ----
; Allow a cpu family to override the isa parallel-insns spec.
; ??? Concession to the m32r port which can go away, in time.
parallel-insns
+
+ ; Computed: maximum number of insns which may pass before there
+ ; an insn writes back its output operands.
+ max-delay
+
)
nil)
)
; Accessors.
! (define-getters <cpu> cpu (word-bitsize insn-chunk-bitsize file-transform parallel-insns max-delay))
! (define-setters <cpu> cpu (max-delay))
; Return endianness of instructions.
***************
*** 1211,1217 ****
word-bitsize
insn-chunk-bitsize
file-transform
! parallel-insns)
(begin
(logit 2 "Ignoring " name ".\n")
#f))) ; cpu is not to be kept
--- 1217,1225 ----
word-bitsize
insn-chunk-bitsize
file-transform
! parallel-insns
! 0 ; default max-delay. will compute correct value
! )
(begin
(logit 2 "Ignoring " name ".\n")
#f))) ; cpu is not to be kept
Index: cgen/operand.scm
===================================================================
RCS file: /cvs/src/src/cgen/operand.scm,v
retrieving revision 1.9
diff -c -p -r1.9 operand.scm
*** cgen/operand.scm 16 Feb 2005 19:45:36 -0000 1.9
--- cgen/operand.scm 15 Jun 2005 20:58:25 -0000
***************
*** 90,95 ****
--- 90,98 ----
; referenced. #f means the operand is always referenced by
; the instruction.
(cond? . #f)
+
+ ; whether (and by how much) this instance of the operand is delayed.
+ (delayed . #f)
)
nil)
)
***************
*** 135,140 ****
--- 138,145 ----
(define op:set-num! (elm-make-setter <operand> 'num))
(define op:cond? (elm-make-getter <operand> 'cond?))
(define op:set-cond?! (elm-make-setter <operand> 'cond?))
+ (define op:delay (elm-make-getter <operand> 'delayed))
+ (define op:set-delay! (elm-make-setter <operand> 'delayed))
; Compute the hardware type lazily.
; FIXME: op:type should be named op:hwtype or some such.
Index: cgen/rtl-c.scm
===================================================================
RCS file: /cvs/src/src/cgen/rtl-c.scm,v
retrieving revision 1.5
diff -c -p -r1.5 rtl-c.scm
*** cgen/rtl-c.scm 16 Jul 2003 05:35:47 -0000 1.5
--- cgen/rtl-c.scm 15 Jun 2005 20:58:26 -0000
***************
*** 1305,1311 ****
"bad arg to `operand'" object-or-name)))
)
! (define-fn xop (estate options mode object) object)
(define-fn local (estate options mode object-or-name)
(cond ((rtx-temp? object-or-name)
--- 1305,1327 ----
"bad arg to `operand'" object-or-name)))
)
! (define-fn xop (estate options mode object)
! (let ((delayed (assoc '#:delay (estate-modifiers estate))))
! (if (and delayed
! (equal? APPLICATION 'SID-SIMULATOR)
! (operand? object))
! ;; if we're looking at an operand inside a (delay ...) rtx, then we
! ;; are talking about a _delayed_ operand, which is a different
! ;; beast. rather than try to work out what context we were
! ;; constructed within, we just clone the operand instance and set
! ;; the new one to have a delayed value. the setters and getters
! ;; will work it out.
! (let ((obj (object-copy object))
! (amount (cadr delayed)))
! (op:set-delay! obj amount)
! obj)
! ;; else return the normal object
! object)))
(define-fn local (estate options mode object-or-name)
(cond ((rtx-temp? object-or-name)
***************
*** 1364,1372 ****
(cx:make VOID "; /*clobber*/\n")
)
! (define-fn delay (estate options mode n rtx)
! (s-sequence (estate-with-modifiers estate '((#:delay))) VOID '() rtx) ; wip!
! )
; Gets expanded as a macro.
;(define-fn annul (estate yes?)
--- 1380,1417 ----
(cx:make VOID "; /*clobber*/\n")
)
!
! (define-fn delay (estate options mode num-node rtx)
! (case APPLICATION
! ((SID-SIMULATOR)
! (let* ((n (cadddr num-node))
! (old-delay (let ((old (assoc '#:delay (estate-modifiers estate))))
! (if old (cadr old) 0)))
! (new-delay (+ n old-delay)))
! (begin
! ;; check for proper usage
! (if (let* ((hw (case (car rtx)
! ((operand) (op:type (rtx-operand-obj rtx)))
! ((xop) (op:type (rtx-xop-obj rtx)))
! (else #f))))
! (not (and hw (or (pc? hw) (memory? hw) (register? hw)))))
! (context-error
! (estate-context estate)
! (string-append
! "(delay ...) rtx applied to wrong type of operand '" (car rtx) "'. should be pc, register or memory")))
! ;; signal an error if we're delayed and not in a "parallel-insns" CPU
! (if (not (with-parallel?))
! (context-error
! (estate-context estate)
! "delayed operand in a non-parallel cpu"))
! ;; update cpu-global pipeline bound
! (cpu-set-max-delay! (current-cpu) (max (cpu-max-delay (current-cpu)) new-delay))
! ;; pass along new delay to embedded rtx
! (rtx-eval-with-estate rtx mode (estate-with-modifiers estate `((#:delay ,new-delay)))))))
!
! ;; not in sid-land
! (else (s-sequence (estate-with-modifiers estate '((#:delay))) VOID '() rtx))))
!
; Gets expanded as a macro.
;(define-fn annul (estate yes?)
Index: cgen/sid-cpu.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid-cpu.scm,v
retrieving revision 1.11
diff -c -p -r1.11 sid-cpu.scm
*** cgen/sid-cpu.scm 16 Jul 2003 05:35:47 -0000 1.11
--- cgen/sid-cpu.scm 15 Jun 2005 20:58:26 -0000
***************
*** 1,5 ****
; CPU family related simulator generator, excluding decoding and model support.
! ; Copyright (C) 2000, 2002 Red Hat, Inc.
; This file is part of CGEN.
; ***********
--- 1,5 ----
; CPU family related simulator generator, excluding decoding and model support.
! ; Copyright (C) 2000, 2002, 2003, 2005 Red Hat, Inc.
; This file is part of CGEN.
; ***********
*************** namespace @arch@ {
*** 199,204 ****
--- 199,282 ----
(-gen-hardware-struct #f (find hw-need-storage? (current-hw-list))))
)
+ (define (-gen-hw-stream-and-destream-fns)
+ (let* ((sa string-append)
+ (regs (find hw-need-storage? (current-hw-list)))
+ (reg-dim (lambda (r)
+ (let ((dims (-hw-vector-dims r)))
+ (if (equal? 0 (length dims))
+ "0"
+ (number->string (car dims))))))
+ (write-stacks
+ (map (lambda (n) (sa n "_writes"))
+ (append (map (lambda (r) (gen-c-symbol (obj:name r))) regs)
+ (map (lambda (m) (sa m "_memory")) useful-mode-names))))
+ (stream-reg (lambda (r)
+ (let ((rname (sa "hardware." (gen-c-symbol (obj:name r)))))
+ (if (hw-scalar? r)
+ (sa " ost << " rname " << ' ';\n")
+ (sa " for (int i = 0; i < " (reg-dim r)
+ "; i++)\n ost << " rname "[i] << ' ';\n")))))
+ (destream-reg (lambda (r)
+ (let ((rname (sa "hardware." (gen-c-symbol (obj:name r)))))
+ (if (hw-scalar? r)
+ (sa " ist >> " rname ";\n")
+ (sa " for (int i = 0; i < " (reg-dim r)
+ "; i++)\n ist >> " rname "[i];\n")))))
+ (stream-stacks (lambda (s) (sa " stream_stacks ( stacks." s ", ost);\n")))
+ (destream-stacks (lambda (s) (sa " destream_stacks ( stacks." s ", ist);\n")))
+ (stack-boilerplate
+ (sa
+ " template <typename ST> \n"
+ " void stream_stacks (const ST &st, std::ostream &ost) const\n"
+ " {\n"
+ " for (int i = 0; i < @prefix@::pipe_sz; i++)\n"
+ " {\n"
+ " ost << st[i].t << ' ';\n"
+ " for (int j = 0; j <= st[i].t; j++)\n"
+ " {\n"
+ " ost << st[i].buf[j].pc << ' ';\n"
+ " ost << st[i].buf[j].val << ' ';\n"
+ " ost << st[i].buf[j].idx0 << ' ';\n"
+ " }\n"
+ " }\n"
+ " }\n"
+ " \n"
+ " template <typename ST> \n"
+ " void destream_stacks (ST &st, std::istream &ist)\n"
+ " {\n"
+ " for (int i = 0; i < @prefix@::pipe_sz; i++)\n"
+ " {\n"
+ " ist >> st[i].t;\n"
+ " for (int j = 0; j <= st[i].t; j++)\n"
+ " {\n"
+ " ist >> st[i].buf[j].pc;\n"
+ " ist >> st[i].buf[j].val;\n"
+ " ist >> st[i].buf[j].idx0;\n"
+ " }\n"
+ " }\n"
+ " }\n"
+ " \n")))
+ (sa
+ " void stream_cgen_hardware (std::ostream &ost) const \n {\n"
+ (string-map stream-reg regs)
+ " }\n"
+ " void destream_cgen_hardware (std::istream &ist) \n {\n"
+ (string-map destream-reg regs)
+ " }\n"
+ (if (with-parallel?)
+ (sa stack-boilerplate
+ " void stream_cgen_write_stacks (std::ostream &ost, "
+ "const @prefix@::write_stacks &stacks) const \n {\n"
+ (string-map stream-stacks write-stacks)
+ " }\n"
+ " void destream_cgen_write_stacks (std::istream &ist, "
+ "@prefix@::write_stacks &stacks) \n {\n"
+ (string-map destream-stacks write-stacks)
+ " }\n")
+ ""))))
+
+
; Generate <cpu>-cpu.h
(define (cgen-cpu.h)
*************** public:
*** 222,227 ****
--- 300,307 ----
-gen-hardware-types
+ -gen-hw-stream-and-destream-fns
+
" // C++ register access function templates\n"
"#define current_cpu this\n\n"
(lambda ()
*************** typedef struct {
*** 295,362 ****
)
)
! ; Utility of gen-parallel-exec-type to generate the definition of one
! ; structure in PAREXEC.
! ; SFMT is an <sformat> object.
!
! (define (gen-parallel-exec-elm sfmt)
! (string-append
! " struct { /* " (obj:comment sfmt) " */\n"
! (let ((sem-ops
! ((if (with-parallel-write?) sfmt-out-ops sfmt-in-ops) sfmt)))
! (if (null? sem-ops)
! " int empty;\n"
! (string-map
! (lambda (op)
! (logit 2 "Processing operand " (obj:name op) " of format "
! (obj:name sfmt) " ...\n")
! (if (with-parallel-write?)
! (let ((index-type (and (op-save-index? op)
! (gen-index-type op sfmt))))
! (string-append " " (gen-type op)
! " " (gen-sym op) ";\n"
! (if index-type
! (string-append " " index-type
! " " (gen-sym op) "_idx;\n")
! "")))
! (string-append " "
! (gen-type op)
! " "
! (gen-sym op)
! ";\n")))
! sem-ops)))
! " } " (gen-sym sfmt) ";\n"
! )
! )
; Generate the definition of the structure that holds register values, etc.
! ; for use during parallel execution. When instructions are executed parallelly
! ; either
! ; - their inputs are read before their outputs are written. Thus we have to
! ; fetch the input values of several instructions before executing any of them.
! ; - or their outputs are queued here first and then written out after all insns
! ; have executed.
! ; The fetched/queued values are stored in an array of PAREXEC structs, one
! ; element per instruction.
! (define (gen-parallel-exec-type)
! (logit 2 "Generating PAREXEC type ...\n")
! (string-append
! (if (with-parallel-write?)
! "/* Queued output values of an instruction. */\n"
! "/* Fetched input values of an instruction. */\n")
! "\
! struct @prefix@_parexec {
! union {\n"
! (string-map gen-parallel-exec-elm (current-sfmt-list))
! "\
! } operands;
! /* For conditionally written operands, bitmask of which ones were. */
! unsigned long long written;
! };\n\n"
! )
! )
; Generate the TRACE_RECORD struct definition.
--- 375,524 ----
)
)
! ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
! ;;; begin stack-based write schedule
! ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
!
! (define useful-mode-names '(BI QI HI SI DI UQI UHI USI UDI SF DF))
!
! (define (-calculated-memory-write-buffer-size)
! (let* ((is-mem? (lambda (op) (eq? (hw-sem-name (op:type op)) 'h-memory)))
! (count-mem-writes
! (lambda (sfmt) (length (find is-mem? (sfmt-out-ops sfmt))))))
! (apply max (append '(0) (map count-mem-writes (current-sfmt-list))))))
!
!
! ;; note: this doesn't really correctly approximate the worst case. user-supplied functions
! ;; might rewrite the pipeline extensively while it's running.
! ;(define (-worst-case-number-of-writes-to hw-name)
! ; (let* ((sfmts (current-sfmt-list))
! ; (out-ops (map sfmt-out-ops sfmts))
! ; (pred (lambda (op) (equal? hw-name (gen-c-symbol (obj:name (op:type op))))))
! ; (filtered-ops (map (lambda (ops) (find pred ops)) out-ops)))
! ; (apply max (cons 0 (map (lambda (ops) (length ops)) filtered-ops)))))
!
! (define (-hw-gen-write-stack-decl nm mode)
! (let* (
! ; for the time being, we're disabling this size-estimation stuff and just
! ; requiring the user to supply a parameter WRITE_BUF_SZ before they include -defs.h
! ; (pipe-sz (+ 1 (max-delay (cpu-max-delay (current-cpu)))))
! ; (sz (* pipe-sz (-worst-case-number-of-writes-to nm))))
!
! (mode-pad (spaces (- 4 (string-length mode))))
! (stack-name (string-append nm "_writes")))
! (string-append
! " write_stack< write<" mode "> >" mode-pad "\t" stack-name "\t[pipe_sz];\n")))
!
!
! (define (-hw-gen-write-struct-decl)
! (let* ((dims (-worst-case-index-dims))
! (sa string-append)
! (ns number->string)
! (idxs (iota dims))
! (ctor (sa "write (PCADDR _pc, MODE _val"
! (string-map (lambda (x) (sa ", USI _idx" (ns x) "=0")) idxs)
! ") : pc(_pc), val(_val)"
! (string-map (lambda (x) (sa ", idx" (ns x) "(_idx" (ns x) ")")) idxs)
! " {} \n"))
! (idx-fields (string-map (lambda (x) (sa " USI idx" (ns x) ";\n")) idxs)))
! (sa
! "\n\n"
! " template <typename MODE>\n"
! " struct write\n"
! " {\n"
! " USI pc;\n"
! " MODE val;\n"
! idx-fields
! " " ctor
! " write() {}\n"
! " };\n" )))
!
! (define (-hw-vector-dims hw) (elm-get (hw-type hw) 'dimensions))
! (define (-worst-case-index-dims)
! (apply max
! (append '(1) ; for memory accesses
! (map (lambda (hw) (length (-hw-vector-dims hw)))
! (find (lambda (hw) (not (scalar? hw))) (current-hw-list))))))
!
!
! (define (-gen-writestacks)
! (let* ((hw (find register? (current-hw-list)))
! (modes useful-mode-names)
! (hw-pairs (map (lambda (h) (list (gen-c-symbol (obj:name h))
! (obj:name (hw-mode h))))
! hw))
! (mem-pairs (map (lambda (m) (list (string-append (symbol->string m)
! "_memory") m))
! modes))
! (all-pairs (append mem-pairs hw-pairs))
!
! (h1 "\n\n// write stacks used in parallel execution\n\n struct write_stacks\n {\n // types of stacks\n\n")
! (wb (string-append
! "\n\n // unified writeback function (defined in @prefix@-write.cc)"
! "\n void writeback (int tick, @cpu@::@cpu@_cpu* current_cpu);"
! "\n // unified write-stack clearing function (defined in @prefix@-write.cc)"
! "\n void reset ();"))
! (zz "\n\n }; // end struct @prefix@::write_stacks \n\n"))
! (string-append
! (-hw-gen-write-struct-decl)
! (foldl (lambda (s pair) (string-append s (apply -hw-gen-write-stack-decl pair))) h1 all-pairs)
! wb
! zz)))
!
! ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
! ;;; end stack-based write schedule
! ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
!
; Generate the definition of the structure that holds register values, etc.
! ; for use during parallel execution.
! (define (gen-write-stack-structure)
! (let ((membuf-sz (-calculated-memory-write-buffer-size))
! (max-delay (cpu-max-delay (current-cpu))))
! (logit 2 "Generating write stack structure ...\n")
! (string-append
! " static const int max_delay = "
! (number->string max-delay) ";\n"
! " static const int pipe_sz = "
! (number->string (+ 1 max-delay)) "; // max_delay + 1\n"
! "
! template <typename ELT>
! struct write_stack
! {
! int t;
! const int sz;
! ELT buf[WRITE_BUF_SZ];
!
! write_stack () : t(-1), sz(WRITE_BUF_SZ) {}
! inline bool empty () { return (t == -1); }
! inline void clear () { t = -1; }
! inline void pop () { if (t > -1) t--;}
! inline void push (const ELT &e) { if (t+1 < sz) buf [++t] = e;}
! inline ELT &top () { return buf [t>0 ? ( t<sz ? t : sz-1) : 0];}
! };
!
! // look ahead for latest write with index = idx, where time of write is
! // <= dist steps from base (present) in write_stack array st.
! // returning def if no scheduled write is found.
!
! template <typename STKS, typename VAL>
! inline VAL lookahead (int dist, int base, STKS &st, VAL def, int idx=0)
! {
! for (; dist > 0; --dist)
! {
! write_stack <VAL> &v = st [(base + dist) % pipe_sz];
! for (int i = v.t; i > 0; --i)
! if (v.buf [i].idx0 == idx) return v.buf [i];
! }
! return def;
! }
!
! "
!
! (-gen-writestacks)
! )))
; Generate the TRACE_RECORD struct definition.
*************** typedef struct @prefix@_trace_record {
*** 392,406 ****
#ifndef DEFS_@PREFIX@_H
#define DEFS_@PREFIX@_H
namespace @cpu@ {
! \n"
! (if (with-parallel?)
! gen-parallel-exec-type
! "")
! "\
! } // end @cpu@ namespace
#endif /* DEFS_@PREFIX@_H */\n"
)
--- 554,580 ----
#ifndef DEFS_@PREFIX@_H
#define DEFS_@PREFIX@_H
+ ")
+ (if (with-parallel?)
+ (string-write "\
+ #include <stack>
+ #include \"cgen-types.h\"
+
+ // forward declaration\n\n
namespace @cpu@ {
! struct @cpu@_cpu;
! }
! namespace @prefix@ {
! using namespace cgen;
!
! "
! gen-write-stack-structure
! "\
! } // end @prefix@ namespace
! "))
! (string-write "\
#endif /* DEFS_@PREFIX@_H */\n"
)
*************** namespace @cpu@ {
*** 417,463 ****
; Return C code to fetch and save all output operands to instructions with
; <sformat> SFMT.
- (define (-gen-write-args sfmt)
- (string-map (lambda (op) (op:write op sfmt))
- (sfmt-out-ops sfmt))
- )
-
- ; Utility of gen-write-fns to generate a writer function for <sformat> SFMT.
! (define (-gen-write-fn sfmt)
! (logit 2 "Processing write function for \"" (obj:name sfmt) "\" ...\n")
! (string-list
! "\nsem_status\n"
! (-gen-write-fn-name sfmt) " (@cpu@_cpu* current_cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec)\n"
! "{\n"
! (if (with-scache?)
! (gen-define-field-macro sfmt)
! "")
! (gen-define-parallel-operand-macro sfmt)
! " @prefix@_scache* abuf = sem;\n"
! " unsigned long long written = abuf->written;\n"
! " PCADDR pc = abuf->addr;\n"
! " PCADDR npc = 0; // dummy value for branches\n"
! " sem_status status = SEM_STATUS_NORMAL; // ditto\n"
! "\n"
! (-gen-write-args sfmt)
! "\n"
! " return status;\n"
! (gen-undef-parallel-operand-macro sfmt)
! (if (with-scache?)
! (gen-undef-field-macro sfmt)
! "")
! "}\n\n")
! )
! (define (-gen-write-fns)
! (logit 2 "Processing writer functions ...\n")
! (string-write-map (lambda (sfmt) (-gen-write-fn sfmt))
! (current-sfmt-list))
! )
! ; Generate <cpu>-write.cxx.
(define (cgen-write.cxx)
(logit 1 "Generating " (gen-cpu-name) " write.cxx ...\n")
--- 591,670 ----
; Return C code to fetch and save all output operands to instructions with
; <sformat> SFMT.
! ; Generate <cpu>-write.cxx.
! (define (-gen-register-writer nm mode dims)
! (let* ((pad " ")
! (sa string-append)
! (mode (symbol->string mode))
! (idx-args (string-map (lambda (x) (sa "w.idx" (number->string x) ", "))
! (iota dims))))
! (sa pad "while (! " nm "_writes[tick].empty())\n"
! pad "{\n"
! pad " write<" mode "> &w = " nm "_writes[tick].top();\n"
! pad " current_cpu->" nm "_set(" idx-args "w.val);\n"
! pad " " nm "_writes[tick].pop();\n"
! pad "}\n\n")))
!
! (define (-gen-memory-writer nm mode dims)
! (let* ((pad " ")
! (sa string-append)
! (mode (symbol->string mode))
! (idx-args (string-map (lambda (x) (sa ", w.idx" (number->string x) ""))
! (iota dims))))
! (sa pad "while (! " nm "_writes[tick].empty())\n"
! pad "{\n"
! pad " write<" mode "> &w = " nm "_writes[tick].top();\n"
! pad " current_cpu->SETMEM" mode " (w.pc" idx-args ", w.val);\n"
! pad " " nm "_writes[tick].pop();\n"
! pad "}\n\n")))
!
!
! (define (-gen-reset-fn)
! (let* ((sa string-append)
! (objs (append (map (lambda (h) (gen-c-symbol (obj:name h)))
! (find register? (current-hw-list)))
! (map (lambda (m) (sa (symbol->string m) "_memory"))
! useful-mode-names)))
! (clr (lambda (elt) (sa " clear_stacks (" elt "_writes);\n"))))
! (sa
! " template <typename ST> \n"
! " static void clear_stacks (ST &st)\n"
! " {\n"
! " for (int i = 0; i < @prefix@::pipe_sz; i++)\n"
! " st[i].clear();\n"
! " }\n\n"
! " void @prefix@::write_stacks::reset ()\n {\n"
! (string-map clr objs)
! " }")))
!
! (define (-gen-unified-write-fn)
! (let* ((hw (find register? (current-hw-list)))
! (modes useful-mode-names)
! (hw-triples (map (lambda (h) (list (gen-c-symbol (obj:name h))
! (obj:name (hw-mode h))
! (length (-hw-vector-dims h))))
! hw))
! (mem-triples (map (lambda (m) (list (string-append (symbol->string m)
! "_memory")
! m 1))
! modes)))
+ (logit 2 "Generating writer function ...\n")
+ (string-append
+ "
! void @prefix@::write_stacks::writeback (int tick, @cpu@::@cpu@_cpu* current_cpu)
! {
! "
! "\n // register writeback loops\n"
! (string-map (lambda (t) (apply -gen-register-writer t)) hw-triples)
! "\n // memory writeback loops\n"
! (string-map (lambda (t) (apply -gen-memory-writer t)) mem-triples)
! "
! }
! ")))
(define (cgen-write.cxx)
(logit 1 "Generating " (gen-cpu-name) " write.cxx ...\n")
*************** namespace @cpu@ {
*** 479,488 ****
"\
#include \"@cpu@.h\"
- using namespace @cpu@;
"
! -gen-write-fns
)
)
\f
--- 686,695 ----
"\
#include \"@cpu@.h\"
"
! -gen-reset-fn
! -gen-unified-write-fn
)
)
\f
*************** using namespace @cpu@;
*** 522,540 ****
"sem_status\n")
"@prefix@_sem_" (gen-sym insn)
(if (with-parallel?)
! " (@cpu@_cpu* current_cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec)\n"
" (@cpu@_cpu* current_cpu, @prefix@_scache* sem)\n")
"{\n"
(gen-define-field-macro (insn-sfmt insn))
- (if (with-parallel?)
- (gen-define-parallel-operand-macro (insn-sfmt insn))
- "")
" sem_status status = SEM_STATUS_NORMAL;\n"
" @prefix@_scache* abuf = sem;\n"
! ; Unconditionally written operands are not recorded here.
! (if (or (with-profile?) (with-parallel-write?))
! " unsigned long long written = 0;\n"
! "")
; The address of this insn, needed by extraction and semantic code.
; Note that the address recorded in the cpu state struct is not used.
; For faster engines that copy will be out of date.
--- 729,742 ----
"sem_status\n")
"@prefix@_sem_" (gen-sym insn)
(if (with-parallel?)
! (string-append " (@cpu@_cpu* current_cpu, @prefix@_scache* sem, const int tick, \n\t"
! "@prefix@::write_stacks &buf)\n")
" (@cpu@_cpu* current_cpu, @prefix@_scache* sem)\n")
"{\n"
(gen-define-field-macro (insn-sfmt insn))
" sem_status status = SEM_STATUS_NORMAL;\n"
" @prefix@_scache* abuf = sem;\n"
!
; The address of this insn, needed by extraction and semantic code.
; Note that the address recorded in the cpu state struct is not used.
; For faster engines that copy will be out of date.
*************** using namespace @cpu@;
*** 543,567 ****
"\n"
(gen-semantic-code insn)
"\n"
- ; Only update what's been written if some are conditionally written.
- ; Otherwise we know they're all written so there's no point in
- ; keeping track.
- (if (or (with-profile?) (with-parallel-write?))
- (if (-any-cond-written? (insn-sfmt insn))
- " abuf->written = written;\n"
- "")
- "")
(if cti?
" current_cpu->done_cti_insn (npc, status);\n"
" current_cpu->done_insn (npc, status);\n")
(if (with-parallel?)
""
" return status;\n")
- (if (with-parallel?)
- (gen-undef-parallel-operand-macro (insn-sfmt insn))
- "")
(gen-undef-field-macro (insn-sfmt insn))
! "}\n\n"
))
)
--- 745,758 ----
"\n"
(gen-semantic-code insn)
"\n"
(if cti?
" current_cpu->done_cti_insn (npc, status);\n"
" current_cpu->done_insn (npc, status);\n")
(if (with-parallel?)
""
" return status;\n")
(gen-undef-field-macro (insn-sfmt insn))
! "}\n\n"
))
)
*************** using namespace @cpu@; // FIXME: namespa
*** 659,667 ****
(if (with-scache?)
(gen-define-field-macro (insn-sfmt insn))
"")
- (if parallel?
- (gen-define-parallel-operand-macro (insn-sfmt insn))
- "")
; Unconditionally written operands are not recorded here.
(if (or (with-profile?) (with-parallel-write?))
" unsigned long long written = 0;\n"
--- 850,855 ----
*************** using namespace @cpu@; // FIXME: namespa
*** 698,706 ****
(string-append " pbb_br_npc = npc;\n"
" pbb_br_status = br_status;\n")
"")
- (if parallel?
- (gen-undef-parallel-operand-macro (insn-sfmt insn))
- "")
(if (with-scache?)
(gen-undef-field-macro (insn-sfmt insn))
"")
--- 886,891 ----
*************** struct @prefix@_pbb_label {
*** 954,962 ****
" vpc = vpc + 1;\n")
"")
(gen-define-field-macro (sfrag-sfmt frag))
- (if parallel?
- (gen-define-parallel-operand-macro (sfrag-sfmt frag))
- "")
; Unconditionally written operands are not recorded here.
(if (or (with-profile?) (with-parallel-write?))
" unsigned long long written = 0;\n"
--- 1139,1144 ----
*************** struct @prefix@_pbb_label {
*** 997,1005 ****
(string-append " pbb_br_npc = npc;\n"
" pbb_br_status = br_status;\n")
"")
- (if parallel?
- (gen-undef-parallel-operand-macro (sfrag-sfmt frag))
- "")
(gen-undef-field-macro (sfrag-sfmt frag))
" }\n"
(if (sfrag-trailer? frag)
--- 1179,1184 ----
Index: cgen/sid-decode.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid-decode.scm,v
retrieving revision 1.14
diff -c -p -r1.14 sid-decode.scm
*** cgen/sid-decode.scm 26 Oct 2003 19:40:30 -0000 1.14
--- cgen/sid-decode.scm 15 Jun 2005 20:58:26 -0000
*************** bool @prefix@_idesc::idesc_table_initial
*** 47,56 ****
(if pbb?
"0, "
(string-append (-gen-sem-fn-name insn) ", "))
! "")
! (if (with-parallel?)
! (string-append (-gen-write-fn-name sfmt) ", ")
! "")
"\"" (string-upcase name) "\", "
(gen-cpu-insn-enum (current-cpu) insn)
", "
--- 47,53 ----
(if pbb?
"0, "
(string-append (-gen-sem-fn-name insn) ", "))
! "")
"\"" (string-upcase name) "\", "
(gen-cpu-insn-enum (current-cpu) insn)
", "
*************** bool @prefix@_idesc::idesc_table_initial
*** 131,155 ****
)
- ;; and the same for writeback functions
-
- (define (-gen-write-fn-name sfmt)
- (string-append "@prefix@_write_" (gen-sym sfmt))
- )
-
-
- (define (-gen-write-fn-decls)
- (string-write
- "// Decls of each writeback fn.\n\n"
- "using @cpu@::@prefix@_write_fn;\n"
- (string-list-map (lambda (sfmt)
- (string-list "extern @prefix@_write_fn "
- (-gen-write-fn-name sfmt)
- ";\n"))
- (current-sfmt-list))
- "\n"
- )
- )
\f
; idesc, argbuf, and scache types
--- 128,133 ----
*************** struct @cpu@_cpu;
*** 164,177 ****
struct @prefix@_scache;
"
(if (with-parallel?)
! "struct @prefix@_parexec;\n" "")
! (if (with-parallel?)
! "typedef void (@prefix@_sem_fn) (@cpu@_cpu* cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec);"
"typedef sem_status (@prefix@_sem_fn) (@cpu@_cpu* cpu, @prefix@_scache* sem);")
"\n"
- (if (with-parallel?)
- "typedef sem_status (@prefix@_write_fn) (@cpu@_cpu* cpu, @prefix@_scache* sem, @prefix@_parexec* par_exec);"
- "")
"\n"
"
// Instruction descriptor.
--- 142,150 ----
struct @prefix@_scache;
"
(if (with-parallel?)
! "typedef void (@prefix@_sem_fn) (@cpu@_cpu* cpu, @prefix@_scache* sem, int tick, @prefix@::write_stacks &buf);"
"typedef sem_status (@prefix@_sem_fn) (@cpu@_cpu* cpu, @prefix@_scache* sem);")
"\n"
"\n"
"
// Instruction descriptor.
*************** struct @prefix@_idesc {
*** 192,203 ****
@prefix@_sem_fn* execute;\n\n"
"")
- (if (with-parallel?)
- "\
- // scache write executor for this insn
- @prefix@_write_fn* writeback;\n\n"
- "")
-
"\
const char* insn_name;
enum @prefix@_insn_type sem_index;
--- 165,170 ----
*************** struct @prefix@_scache {
*** 300,306 ****
// argument buffer
@prefix@_sem_fields fields;
! " (if (or (with-any-profile?) (with-parallel-write?))
(string-append "
// writeback flags
// Only used if profiling or parallel execution support enabled during
--- 267,273 ----
// argument buffer
@prefix@_sem_fields fields;
! " (if (with-any-profile?)
(string-append "
// writeback flags
// Only used if profiling or parallel execution support enabled during
*************** struct @prefix@_scache {
*** 549,555 ****
(let ((in-ops (find op-profilable? (sfmt-in-ops sfmt)))
(out-ops (find op-profilable? (sfmt-out-ops sfmt)))
)
! (if (and (null? in-ops) (null? out-ops))
""
(string-list
" /* Record the fields for profiling. */\n"
--- 516,522 ----
(let ((in-ops (find op-profilable? (sfmt-in-ops sfmt)))
(out-ops (find op-profilable? (sfmt-out-ops sfmt)))
)
! (if (or (not (with-any-profile?)) (and (null? in-ops) (null? out-ops)))
""
(string-list
" /* Record the fields for profiling. */\n"
*************** void
*** 714,719 ****
--- 681,697 ----
#ifndef @PREFIX@_DECODE_H
#define @PREFIX@_DECODE_H
+ "
+ (if (with-parallel?)
+ "\
+ namespace @prefix@ {
+ // forward declaration of struct in -defs.h
+ struct write_stacks;
+ }
+
+ "
+ "")
+ "\
namespace @cpu@ {
using namespace cgen;
*************** typedef UINT @prefix@_insn_word;
*** 737,746 ****
-gen-sem-fn-decls
"")
- (if (with-parallel?)
- -gen-write-fn-decls
- "")
-
"\
#endif /* @PREFIX@_DECODE_H */\n"
)
--- 715,720 ----
Index: cgen/sid.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid.scm,v
retrieving revision 1.14
diff -c -p -r1.14 sid.scm
*** cgen/sid.scm 17 May 2005 01:47:16 -0000 1.14
--- cgen/sid.scm 15 Jun 2005 20:58:26 -0000
***************
*** 931,973 ****
(rtl-c++ INT yes? nil #:rtl-cover-fns? #t)))
)
- ; For parallel write post-processing, we don't want to defer setting the pc.
- ; ??? Not sure anymore.
- ;(method-make!
- ; <pc> 'gen-set-quiet
- ; (lambda (self estate mode index selector newval)
- ; (-op-gen-set-quiet self estate mode index selector newval)))
- ;(method-make!
- ; <pc> 'gen-set-trace
- ; (lambda (self estate mode index selector newval)
- ; (-op-gen-set-trace self estate mode index selector newval)))
-
- ; Name of C macro to access parallel execution operand support.
-
- (define -par-operand-macro "OPRND")
-
- ; Return C code to fetch an operand's value and save it away for the
- ; semantic handler. This is used to handle parallel execution of several
- ; instructions where all inputs of all insns are read before any outputs are
- ; written.
- ; For operands, the word `read' is only used in this context.
-
- (define (op:read op sfmt)
- (let ((estate (estate-make-for-normal-rtl-c++ nil nil)))
- (send op 'gen-read estate sfmt -par-operand-macro))
- )
-
- ; Return C code to write an operand's value.
- ; This is used to handle parallel execution of several instructions where all
- ; outputs are written to temporary spots first, and then a final
- ; post-processing pass is run to update cpu state.
- ; For operands, the word `write' is only used in this context.
-
- (define (op:write op sfmt)
- (let ((estate (estate-make-for-normal-rtl-c++ nil nil)))
- (send op 'gen-write estate sfmt -par-operand-macro))
- )
-
; Default gen-read method.
; This is used to help support targets with parallel insns.
; Either this or gen-write (but not both) is used.
--- 931,936 ----
***************
*** 1017,1052 ****
(method-make!
<operand> 'cxmake-get
(lambda (self estate mode index selector)
! (let ((mode (if (mode:eq? 'DFLT mode)
! (send self 'get-mode)
! mode))
! (index (if index index (op:index self)))
! (selector (if selector selector (op:selector self))))
! ; If the object is marked with the RAW attribute, access the hardware
! ; object directly.
(logit 4 "<operand> cxmake-get self=" (obj:name self) " mode=" (obj:name mode)
" index=" (obj:name index) " selector=" selector "\n")
! (cond ((obj-has-attr? self 'RAW)
! (send (op:type self) 'cxmake-get-raw estate mode index selector))
! ; If the instruction could be parallely executed with others and
! ; we're doing read pre-processing, the operand has already been
! ; fetched, we just have to grab the cached value.
! ((with-parallel-read?)
! (cx:make-with-atlist mode
! (string-append -par-operand-macro
! " (" (gen-sym self) ")")
! nil)) ; FIXME: want CACHED attr if present
! ((op:getter self)
! (let ((args (car (op:getter self)))
! (expr (cadr (op:getter self))))
! (rtl-c-expr mode expr
! (if (= (length args) 0)
! nil
! (list (list (car args) 'UINT index)))
! #:rtl-cover-fns? #t
! #:output-language (estate-output-language estate))))
! (else
! (send (op:type self) 'cxmake-get estate mode index selector)))))
)
--- 980,1024 ----
(method-make!
<operand> 'cxmake-get
(lambda (self estate mode index selector)
! (let* ((mode (if (mode:eq? 'DFLT mode)
! (send self 'get-mode)
! mode))
! (hw (op:type self))
! (index (if index index (op:index self)))
! (idx (if index (-gen-hw-index index estate) ""))
! (idx-args (if (equal? idx "") "" (string-append ", " idx)))
! (selector (if selector selector (op:selector self)))
! (delayval (op:delay self))
! (md (mode:c-type mode))
! (name (if
! (eq? (obj:name hw) 'h-memory)
! (string-append md "_memory")
! (gen-c-symbol (obj:name hw))))
! (getter (op:getter self))
! (def-val (cond ((obj-has-attr? self 'RAW)
! (send hw 'cxmake-get-raw estate mode index selector))
! (getter
! (let ((args (car getter))
! (expr (cadr getter)))
! (rtl-c-expr mode expr
! (if (= (length args) 0) nil
! (list (list (car args) 'UINT index)))
! #:rtl-cover-fns? #t
! #:output-language (estate-output-language estate))))
! (else
! (send hw 'cxmake-get estate mode index selector)))))
!
(logit 4 "<operand> cxmake-get self=" (obj:name self) " mode=" (obj:name mode)
" index=" (obj:name index) " selector=" selector "\n")
!
! (if delayval
! (cx:make mode (string-append "lookahead ("
! (number->string delayval)
! ", tick, "
! "buf." name "_writes, "
! (cx:c def-val)
! idx-args ")"))
! def-val)))
)
***************
*** 1056,1071 ****
(send (op:type op) 'gen-set-quiet estate mode index selector newval)
)
! (define (-op-gen-set-quiet-parallel op estate mode index selector newval)
! (string-append
! (if (op-save-index? op)
! (string-append " " -par-operand-macro " (" (-op-index-name op) ")"
! " = " (-gen-hw-index index estate) ";\n")
! "")
! " "
! -par-operand-macro " (" (gen-sym op) ")"
! " = " (cx:c newval) ";\n")
! )
(define (-op-gen-set-trace op estate mode index selector newval)
(string-append
--- 1028,1036 ----
(send (op:type op) 'gen-set-quiet estate mode index selector newval)
)
! (define (-op-gen-delayed-set-quiet op estate mode index selector newval)
! (-op-gen-delayed-set-maybe-trace op estate mode index selector newval #f))
!
(define (-op-gen-set-trace op estate mode index selector newval)
(string-append
***************
*** 1129,1143 ****
" }\n")
)
! (define (-op-gen-set-trace-parallel op estate mode index selector newval)
! (string-append
! " {\n"
! " " (mode:c-type mode) " opval = " (cx:c newval) ";\n"
! (if (op:cond? op)
! (string-append " written |= (1ULL << "
! (number->string (op:num op))
! ");\n")
! "")
; TRACE_RESULT_<MODE> (cpu, abuf, hwnum, opnum, value);
; For each insn record array of operand numbers [or indices into
; operand instance table].
--- 1094,1134 ----
" }\n")
)
! (define (-op-gen-delayed-set-trace op estate mode index selector newval)
! (-op-gen-delayed-set-maybe-trace op estate mode index selector newval #t))
!
! (define (-op-gen-delayed-set-maybe-trace op estate mode index selector newval do-trace?)
! (let* ((pad " ")
! (hw (op:type op))
! (delayval (op:delay op))
! (md (mode:c-type mode))
! (name (if
! (eq? (obj:name hw) 'h-memory)
! (string-append md "_memory")
! (gen-c-symbol (obj:name hw))))
! (val (cx:c newval))
! (idx (if index (-gen-hw-index index estate) ""))
! (idx-args (if (equal? idx "") "" (string-append ", " idx)))
! )
!
! (string-append
! " {\n"
!
! (if delayval
!
! ;; delayed write: push it to the appropriate buffer
! (string-append
! pad md " opval = " val ";\n"
! pad "buf." name "_writes [(tick + " (number->string delayval)
! ") % @prefix@::pipe_sz].push (@prefix@::write<" md ">(pc, opval" idx-args "));\n")
!
! ;; else, uh, we should never have been called!
! (error "-op-gen-delayed-set-maybe-trace called on non-delayed operand"))
!
!
! (if do-trace?
!
! (string-append
; TRACE_RESULT_<MODE> (cpu, abuf, hwnum, opnum, value);
; For each insn record array of operand numbers [or indices into
; operand instance table].
***************
*** 1169,1183 ****
"(USI) "
""))
"opval << dec << \" \";\n"
- (if (op-save-index? op)
- (string-append " " -par-operand-macro " (" (-op-index-name op) ")"
- " = " (-gen-hw-index index estate) ";\n")
- "")
- " " -par-operand-macro " (" (gen-sym op) ")"
- " = opval;\n"
" }\n")
! )
!
; Return C code to set the value of an operand.
; NEWVAL is a <c-expr> object of the value to store.
--- 1160,1168 ----
"(USI) "
""))
"opval << dec << \" \";\n"
" }\n")
! ;; else no tracing is emitted
! ""))))
; Return C code to set the value of an operand.
; NEWVAL is a <c-expr> object of the value to store.
***************
*** 1196,1203 ****
(selector (if selector selector (op:selector self))))
(cond ((obj-has-attr? self 'RAW)
(send (op:type self) 'gen-set-quiet-raw estate mode index selector newval))
! ((with-parallel-write?)
! (-op-gen-set-quiet-parallel self estate mode index selector newval))
(else
(-op-gen-set-quiet self estate mode index selector newval)))))
)
--- 1181,1188 ----
(selector (if selector selector (op:selector self))))
(cond ((obj-has-attr? self 'RAW)
(send (op:type self) 'gen-set-quiet-raw estate mode index selector newval))
! ((op:delay self)
! (-op-gen-delayed-set-quiet self estate mode index selector newval))
(else
(-op-gen-set-quiet self estate mode index selector newval)))))
)
***************
*** 1219,1244 ****
(selector (if selector selector (op:selector self))))
(cond ((obj-has-attr? self 'RAW)
(send (op:type self) 'gen-set-quiet-raw estate mode index selector newval))
! ((with-parallel-write?)
! (-op-gen-set-trace-parallel self estate mode index selector newval))
(else
(-op-gen-set-trace self estate mode index selector newval)))))
)
- ; Define and undefine C macros to tuck away details of instruction format used
- ; in the parallel execution functions. See gen-define-field-macro for a
- ; similar thing done for extraction/semantic functions.
-
- (define (gen-define-parallel-operand-macro sfmt)
- (string-append "#define " -par-operand-macro "(f) "
- "par_exec->operands."
- (gen-sym sfmt)
- ".f\n")
- )
-
- (define (gen-undef-parallel-operand-macro sfmt)
- (string-append "#undef " -par-operand-macro "\n")
- )
\f
; Operand profiling and parallel execution support.
--- 1204,1215 ----
(selector (if selector selector (op:selector self))))
(cond ((obj-has-attr? self 'RAW)
(send (op:type self) 'gen-set-quiet-raw estate mode index selector newval))
! ((op:delay self)
! (-op-gen-delayed-set-trace self estate mode index selector newval))
(else
(-op-gen-set-trace self estate mode index selector newval)))))
)
\f
; Operand profiling and parallel execution support.
Index: cgen/utils.scm
===================================================================
RCS file: /cvs/src/src/cgen/utils.scm,v
retrieving revision 1.17
diff -c -p -r1.17 utils.scm
*** cgen/utils.scm 10 May 2005 10:21:02 -0000 1.17
--- cgen/utils.scm 15 Jun 2005 20:58:26 -0000
***************
*** 563,568 ****
--- 563,584 ----
(reverse! (list-drop n (reverse l)))
)
+ ;; left fold
+ (define (foldl kons accum lis)
+ (if (null? lis) accum
+ (foldl kons (kons accum (car lis)) (cdr lis))))
+
+ ;; right fold
+ (define (foldr kons knil lis)
+ (if (null? lis) knil
+ (kons (car lis) (foldr kons knil (cdr lis)))))
+
+ ;; filter list on predicate
+ (define (filter p ls)
+ (foldr (lambda (x a) (if (p x) (cons x a) a))
+ '() ls))
+
+
; APL's +\ operation on a vector of numbers.
(define (plus-scan l)
***************
*** 635,646 ****
; Return intersection of two lists.
! (define (intersection l1 l2)
! (cond ((null? l1) l1)
! ((null? l2) l2)
! ((memq (car l1) l2) (cons (car l1) (intersection (cdr l1) l2)))
! (else (intersection (cdr l1) l2)))
! )
; Return a count of the number of elements of list L1 that are in list L2.
; Uses memq.
--- 651,663 ----
; Return intersection of two lists.
! (define (intersection a b)
! (foldl (lambda (l e) (if (memq e a) (cons e l) l)) '() b))
!
! ; Return union of two lists.
!
! (define (union a b)
! (foldl (lambda (l e) (if (memq e l) l (cons e l))) a b))
; Return a count of the number of elements of list L1 that are in list L2.
; Uses memq.
Index: cgen/doc/rtl.texi
===================================================================
RCS file: /cvs/src/src/cgen/doc/rtl.texi,v
retrieving revision 1.21
diff -c -p -r1.21 rtl.texi
*** cgen/doc/rtl.texi 10 Jun 2003 22:09:43 -0000 1.21
--- cgen/doc/rtl.texi 15 Jun 2005 20:58:26 -0000
*************** Indicate that there are @samp{num} delay
*** 2271,2276 ****
--- 2271,2310 ----
@samp{expr}. When using this rtx in instruction semantics, CGEN will
infer that the instruction has the DELAY-SLOT attribute.
+ @item (delay num expr)
+ In older "sim" simulators, indicates that there are @samp{num} delay
+ slots in the processing of @samp{expr}. When using this rtx in instruction
+ semantics, CGEN will infer that the instruction has the DELAY-SLOT
+ attribute.
+
+ In newer "sid" simulators, evaluates to the writeback queue for hardware
+ operand @samp{expr}, at @samp{num} instruction cycles in the
+ future. @samp{expr} @emph{must} be a hardware operand in this case.
+
+ For example, @code{(set (delay 3 pc) (+ pc 1))} will schedule write to
+ the @samp{pc} register in the writeback phase of the 3rd instruction
+ after the current. Alternatively, @code{(set gr1 (delay 3 gr2))} will
+ immediately update the @samp{gr1} register with the @emph{latest write}
+ to the @samp{gr2} register scheduled between the present and 3
+ instructions in the future. @code{(delay 0 ...)} refers to the
+ writeback phase of the current instruction.
+
+ This effect is modeled with a circular buffer of "write stacks" for each
+ hardware element (register banks get a single stack). The size of the
+ circular buffer is calculated from the uses of @code{(delay ...)}
+ rtxs. When a delayed write occurs, the simulator pushes the write onto
+ the appropriate write stack in the "future" of the circular buffer for
+ the written-to hardware element. At the end of each instruction cycle,
+ the simulator executes all writes in all write stacks for the time slice
+ just ending. When a delayed read (essentially a pipeline bypass) occurs,
+ the simulator looks ahead in the circular buffer for any writes
+ scheduled in the future write stack. If it doesn't find one, it
+ progressively backs off towards the "current" instruction cycle's write
+ stack, and if it still finds no scheduled writes then it returns the
+ current state of the CPU. Thus while delayed writes are fast, delayed
+ reads are potentially slower in a simulator with long pipelines and very
+ large register banks.
+
@item (annul yes?)
@c FIXME: put annul into the glossary.
Annul the following instruction if @samp{yes?} is non-zero. This rtx is
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-13 14:55 ` Frank Ch. Eigler
2005-06-15 21:37 ` Dave Brolley
@ 2005-06-15 21:39 ` Dave Brolley
1 sibling, 0 replies; 12+ messages in thread
From: Dave Brolley @ 2005-06-15 21:39 UTC (permalink / raw)
To: sid
[-- Attachment #1: Type: text/plain, Size: 291 bytes --]
Frank Ch. Eigler wrote:
>>I will also be submitting the opcodes and SID ports to their
>>respective lists.
>>
>>
>
>With respect to cgen/sid-bound sources, commit at will.
>
>
>
I have committed the attached patch which adds the Morpho ms1 to
sid/component/cgen-cpu.
Regards,
Dave
[-- Attachment #2: sid.ms1.ChangeLog --]
[-- Type: text/plain, Size: 299 bytes --]
2005-06-15 Dave Brolley <brolley@redhat.com>
Morpho ms1 cpu contributed on behalf of Red Hat
2004-05-14 Stan Cox <scox@redhat.com>
* ms1: New directory.
* aclocal.m4: Regenerated.
* Makefile.in: Ditto.
* configure: Ditto.
* configure.in: Support added for ms1.
* compCGEN.cxx: Ditto.
[-- Attachment #3: sid.ms1.patch.txt --]
[-- Type: text/plain, Size: 5118 bytes --]
Index: sid/component/cgen-cpu/Makefile.in
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/Makefile.in,v
retrieving revision 1.13
diff -c -p -r1.13 Makefile.in
*** sid/component/cgen-cpu/Makefile.in 4 Jun 2005 03:23:02 -0000 1.13
--- sid/component/cgen-cpu/Makefile.in 15 Jun 2005 21:18:10 -0000
*************** SIDTARGET_M32R_FALSE = @SIDTARGET_M32R_F
*** 182,187 ****
--- 182,189 ----
SIDTARGET_M32R_TRUE = @SIDTARGET_M32R_TRUE@
SIDTARGET_M68K_FALSE = @SIDTARGET_M68K_FALSE@
SIDTARGET_M68K_TRUE = @SIDTARGET_M68K_TRUE@
+ SIDTARGET_MS1_FALSE = @SIDTARGET_MS1_FALSE@
+ SIDTARGET_MS1_TRUE = @SIDTARGET_MS1_TRUE@
SIDTARGET_MIPS_FALSE = @SIDTARGET_MIPS_FALSE@
SIDTARGET_MIPS_TRUE = @SIDTARGET_MIPS_TRUE@
SIDTARGET_PPC_FALSE = @SIDTARGET_PPC_FALSE@
*************** sharedstatedir = @sharedstatedir@
*** 244,249 ****
--- 246,252 ----
sidtarget_arm = @sidtarget_arm@
sidtarget_m32r = @sidtarget_m32r@
sidtarget_m68k = @sidtarget_m68k@
+ sidtarget_ms1 = @sidtarget_ms1@
sidtarget_mips = @sidtarget_mips@
sidtarget_ppc = @sidtarget_ppc@
sidtarget_x86 = @sidtarget_x86@
Index: sid/component/cgen-cpu/aclocal.m4
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/aclocal.m4,v
retrieving revision 1.6
diff -c -p -r1.6 aclocal.m4
*** sid/component/cgen-cpu/aclocal.m4 4 Jun 2005 03:23:02 -0000 1.6
--- sid/component/cgen-cpu/aclocal.m4 15 Jun 2005 21:18:10 -0000
*************** sidtarget_arm=$sidtarget_default
*** 7106,7111 ****
--- 7106,7112 ----
sidtarget_x86=$sidtarget_default
sidtarget_mips=$sidtarget_default
sidtarget_m32r=$sidtarget_default
+ sidtarget_ms1=$sidtarget_default
sidtarget_m68k=$sidtarget_default
sidtarget_ppc=$sidtarget_default
sidtarget_xstormy16=$sidtarget_default
*************** do
*** 7120,7125 ****
--- 7121,7127 ----
mips*) sidtarget_mips=1 ;;
m32r*) sidtarget_m32r=1 ;;
m68k*) sidtarget_m68k=1 ;;
+ ms1*) sidtarget_ms1=1 ;;
powerpc*) sidtarget_ppc=1 ;;
ppc*) sidtarget_ppc=1 ;;
xstormy16*) sidtarget_xstormy16=1 ;;
*************** case 1 in
*** 7134,7139 ****
--- 7136,7142 ----
${sidtarget_mips}) ;;
${sidtarget_m32r}) ;;
${sidtarget_m68k}) ;;
+ ${sidtarget_ms1}) ;;
${sidtarget_ppc}) ;;
${sidtarget_xstormy16}) ;;
*) AC_MSG_WARN([No selected sid targets: use --enable-targets or --target])
*************** AC_SUBST(sidtarget_m68k)
*** 7169,7174 ****
--- 7172,7182 ----
AM_CONDITIONAL(SIDTARGET_M68K,[test "x$sidtarget_m68k" = x1])
AC_MSG_RESULT($sidtarget_m68k)
+ AC_MSG_CHECKING(MS1 family support)
+ AC_SUBST(sidtarget_ms1)
+ AM_CONDITIONAL(SIDTARGET_MS1,[test "x$sidtarget_ms1" = x1])
+ AC_MSG_RESULT($sidtarget_ms1)
+
AC_MSG_CHECKING(PPC family support)
AC_SUBST(sidtarget_ppc)
AM_CONDITIONAL(SIDTARGET_PPC,[test "x$sidtarget_ppc" = x1])
Index: sid/component/cgen-cpu/compCGEN.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/compCGEN.cxx,v
retrieving revision 1.13
diff -c -p -r1.13 compCGEN.cxx
*** sid/component/cgen-cpu/compCGEN.cxx 25 Jun 2004 17:44:35 -0000 1.13
--- sid/component/cgen-cpu/compCGEN.cxx 15 Jun 2005 21:18:10 -0000
*************** extern "C" {
*** 26,31 ****
--- 26,34 ----
#if SIDTARGET_M32R
#include "m32rbf.h"
#endif
+ #if SIDTARGET_MS1
+ #include "ms1.h"
+ #endif
#if SIDTARGET_XSTORMY16
#include "xstormy16.h"
#endif
*************** compCGENListTypes ()
*** 280,285 ****
--- 283,291 ----
#if SIDTARGET_ARM
types.push_back ("hw-cpu-arm7t");
#endif
+ #if SIDTARGET_MS1
+ types.push_back ("hw-cpu-ms1");
+ #endif
#if SIDTARGET_XSTORMY16
types.push_back ("hw-cpu-xstormy16");
#endif
*************** compCGENCreate (const string& typeName)
*** 299,304 ****
--- 305,314 ----
if (typeName == "hw-cpu-arm7t")
return new arm7f::arm7f_cpu ();
#endif
+ #if SIDTARGET_MS1
+ if (typeName == "hw-cpu-ms1")
+ return new ms1::ms1_cpu ();
+ #endif
#if SIDTARGET_XSTORMY16
if (typeName == "hw-cpu-xstormy16")
return new xstormy16::xstormy16_cpu ();
Index: sid/component/cgen-cpu/configure.in
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/configure.in,v
retrieving revision 1.8
diff -c -p -r1.8 configure.in
*** sid/component/cgen-cpu/configure.in 4 Jun 2005 03:23:03 -0000 1.8
--- sid/component/cgen-cpu/configure.in 15 Jun 2005 21:18:11 -0000
*************** if test $sidtarget_m32r -eq 1; then
*** 53,58 ****
--- 53,62 ----
cpu_subdirs="$cpu_subdirs m32r"
AC_CONFIG_SUBDIRS(m32r)
fi
+ if test $sidtarget_ms1 -eq 1; then
+ cpu_subdirs="$cpu_subdirs ms1"
+ AC_CONFIG_SUBDIRS(ms1)
+ fi
if test $sidtarget_xstormy16 -eq 1; then
cpu_subdirs="$cpu_subdirs xstormy16"
AC_CONFIG_SUBDIRS(xstormy16)
*************** for dir in $cpu_subdirs; do
*** 64,69 ****
--- 68,74 ----
done
AC_SUBST(cpu_subdirs)
+ AC_SUBST(cpu_defs)
AC_SUBST(cpu_incl)
AC_SUBST(cpu_libs)
AC_SUBST(cpu_defs)
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-15 21:37 ` Dave Brolley
@ 2005-06-15 21:46 ` Doug Evans
2005-06-16 14:22 ` Dave Brolley
2005-06-16 15:22 ` Frank Ch. Eigler
0 siblings, 2 replies; 12+ messages in thread
From: Doug Evans @ 2005-06-15 21:46 UTC (permalink / raw)
To: Dave Brolley; +Cc: cgen, sid
Eewwwww!
Imagine if bison or autoconf had encoded in them knowledge of particular
applications that used them.
[The analogy doesn't port 1-1, but the eewww-ness is equivalent.]
Dave Brolley writes:
> Index: cgen/rtl-c.scm
> ===================================================================
> RCS file: /cvs/src/src/cgen/rtl-c.scm,v
> retrieving revision 1.5
> diff -c -p -r1.5 rtl-c.scm
> *** cgen/rtl-c.scm 16 Jul 2003 05:35:47 -0000 1.5
> --- cgen/rtl-c.scm 15 Jun 2005 20:58:26 -0000
> ***************
> *** 1305,1311 ****
> "bad arg to `operand'" object-or-name)))
> )
>
> ! (define-fn xop (estate options mode object) object)
>
> (define-fn local (estate options mode object-or-name)
> (cond ((rtx-temp? object-or-name)
> --- 1305,1327 ----
> "bad arg to `operand'" object-or-name)))
> )
>
> ! (define-fn xop (estate options mode object)
> ! (let ((delayed (assoc '#:delay (estate-modifiers estate))))
> ! (if (and delayed
> ! (equal? APPLICATION 'SID-SIMULATOR)
> ! (operand? object))
> ! ;; if we're looking at an operand inside a (delay ...) rtx, then we
> ! ;; are talking about a _delayed_ operand, which is a different
> ! ;; beast. rather than try to work out what context we were
> ! ;; constructed within, we just clone the operand instance and set
> ! ;; the new one to have a delayed value. the setters and getters
> ! ;; will work it out.
> ! (let ((obj (object-copy object))
> ! (amount (cadr delayed)))
> ! (op:set-delay! obj amount)
> ! obj)
> ! ;; else return the normal object
> ! object)))
>
> (define-fn local (estate options mode object-or-name)
> (cond ((rtx-temp? object-or-name)
> ***************
> *** 1364,1372 ****
> (cx:make VOID "; /*clobber*/\n")
> )
>
> ! (define-fn delay (estate options mode n rtx)
> ! (s-sequence (estate-with-modifiers estate '((#:delay))) VOID '() rtx) ; wip!
> ! )
>
> ; Gets expanded as a macro.
> ;(define-fn annul (estate yes?)
> --- 1380,1417 ----
> (cx:make VOID "; /*clobber*/\n")
> )
>
> !
> ! (define-fn delay (estate options mode num-node rtx)
> ! (case APPLICATION
> ! ((SID-SIMULATOR)
> ! (let* ((n (cadddr num-node))
> ! (old-delay (let ((old (assoc '#:delay (estate-modifiers estate))))
> ! (if old (cadr old) 0)))
> ! (new-delay (+ n old-delay)))
> ! (begin
> ! ;; check for proper usage
> ! (if (let* ((hw (case (car rtx)
> ! ((operand) (op:type (rtx-operand-obj rtx)))
> ! ((xop) (op:type (rtx-xop-obj rtx)))
> ! (else #f))))
> ! (not (and hw (or (pc? hw) (memory? hw) (register? hw)))))
> ! (context-error
> ! (estate-context estate)
> ! (string-append
> ! "(delay ...) rtx applied to wrong type of operand '" (car rtx) "'. should be pc, register or memory")))
> ! ;; signal an error if we're delayed and not in a "parallel-insns" CPU
> ! (if (not (with-parallel?))
> ! (context-error
> ! (estate-context estate)
> ! "delayed operand in a non-parallel cpu"))
> ! ;; update cpu-global pipeline bound
> ! (cpu-set-max-delay! (current-cpu) (max (cpu-max-delay (current-cpu)) new-delay))
> ! ;; pass along new delay to embedded rtx
> ! (rtx-eval-with-estate rtx mode (estate-with-modifiers estate `((#:delay ,new-delay)))))))
> !
> ! ;; not in sid-land
> ! (else (s-sequence (estate-with-modifiers estate '((#:delay))) VOID '() rtx))))
> !
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-15 21:46 ` Doug Evans
@ 2005-06-16 14:22 ` Dave Brolley
2005-06-16 15:22 ` Frank Ch. Eigler
1 sibling, 0 replies; 12+ messages in thread
From: Dave Brolley @ 2005-06-16 14:22 UTC (permalink / raw)
To: Doug Evans; +Cc: cgen, sid
Hi Doug,
Certainly some of the scheme code used by CGEN knows exactly what
'application' is using it:
sid*.scm, sim*.scm, cgen-sid.scm, cgen-sim.scm
I guess that with these one would argue that these source files *are*
the 'application'.
What we have here are functions which are called by several
'applications' which to analyse the same data but which require
different output. I imagine that there must be some way to separate the
different logic into the application-specific source files.
My knowledge of scheme isn't the greatest so please do make suggestions!
Thanks,
Dave
Doug Evans wrote:
>Eewwwww!
>
>Imagine if bison or autoconf had encoded in them knowledge of particular
>applications that used them.
>[The analogy doesn't port 1-1, but the eewww-ness is equivalent.]
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-15 21:46 ` Doug Evans
2005-06-16 14:22 ` Dave Brolley
@ 2005-06-16 15:22 ` Frank Ch. Eigler
2005-06-16 15:42 ` Doug Evans
1 sibling, 1 reply; 12+ messages in thread
From: Frank Ch. Eigler @ 2005-06-16 15:22 UTC (permalink / raw)
To: Doug Evans; +Cc: cgen, sid
[-- Attachment #1: Type: text/plain, Size: 399 bytes --]
Hi -
On Wed, Jun 15, 2005 at 02:46:38PM -0700, Doug Evans wrote:
> Imagine if bison or autoconf had encoded in them knowledge of particular
> applications that used them.
> [...]
Well, the RTL model needed extension to allow for delayed operations.
Since this part of the RTL was only used for instruction semantics,
and thus simulators, adding some more specialized code is not that bad.
- FChE
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-16 15:22 ` Frank Ch. Eigler
@ 2005-06-16 15:42 ` Doug Evans
2005-06-16 15:49 ` Frank Ch. Eigler
0 siblings, 1 reply; 12+ messages in thread
From: Doug Evans @ 2005-06-16 15:42 UTC (permalink / raw)
To: Frank Ch. Eigler; +Cc: cgen, sid
Frank Ch. Eigler writes:
> Hi -
>
> On Wed, Jun 15, 2005 at 02:46:38PM -0700, Doug Evans wrote:
> > Imagine if bison or autoconf had encoded in them knowledge of particular
> > applications that used them.
> > [...]
>
> Well, the RTL model needed extension to allow for delayed operations.
> Since this part of the RTL was only used for instruction semantics,
> and thus simulators, adding some more specialized code is not that bad.
- nit: it's not necessarily the case that insn semantics would only
be used by simulators
- e.g. the operand tables derived from insn semantics are used by m32r gas
- even if it were, the patch hardwires the test to SID-SIMULATOR
- adding specialized code can be "that bad" because without adequate
commenting like "do as I say, not as I do", more and more such code
creeps in over time
- imagine if there's 20 different apps (as in (eq? APPLICATION mumble))
all with their own little tweaks to rtl-c.scm
Remove the appearance of the text "SID" from rtl-c.scm and parameterize
the feature on something generic and I'd be happier.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-16 15:42 ` Doug Evans
@ 2005-06-16 15:49 ` Frank Ch. Eigler
2005-06-16 16:04 ` Doug Evans
0 siblings, 1 reply; 12+ messages in thread
From: Frank Ch. Eigler @ 2005-06-16 15:49 UTC (permalink / raw)
To: Doug Evans; +Cc: cgen, sid
[-- Attachment #1: Type: text/plain, Size: 766 bytes --]
Hi -
On Thu, Jun 16, 2005 at 08:41:58AM -0700, Doug Evans wrote:
> [...]
> - adding specialized code can be "that bad" because without adequate
> commenting like "do as I say, not as I do", more and more such code
> creeps in over time
> - imagine if there's 20 different apps (as in (eq? APPLICATION mumble))
> all with their own little tweaks to rtl-c.scm
>
> Remove the appearance of the text "SID" from rtl-c.scm and parameterize
> the feature on something generic and I'd be happier.
These are reasonable concerns in the abstract. Let's not insist on
extra maintenance work on this old code until there is an indication
that another of those 20 different apps shows up, or that gdb/sim will
model delayed writes too.
- FChE
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC] New cpu --- Morpho ms1
2005-06-16 15:49 ` Frank Ch. Eigler
@ 2005-06-16 16:04 ` Doug Evans
0 siblings, 0 replies; 12+ messages in thread
From: Doug Evans @ 2005-06-16 16:04 UTC (permalink / raw)
To: Frank Ch. Eigler; +Cc: cgen, sid
Frank Ch. Eigler writes:
> These are reasonable concerns in the abstract. Let's not insist on
> extra maintenance work on this old code until there is an indication
> that another of those 20 different apps shows up, or that gdb/sim will
> model delayed writes too.
I disagree. There is value in avoiding obviously bad code, especially
instances that set a bad precedent.
I seriously doubt a reasonable solution is non-trivial.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2005-06-16 16:04 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2005-06-08 20:19 [RFC] New cpu --- Morpho ms1 Dave Brolley
2005-06-13 14:55 ` Frank Ch. Eigler
2005-06-15 21:37 ` Dave Brolley
2005-06-15 21:46 ` Doug Evans
2005-06-16 14:22 ` Dave Brolley
2005-06-16 15:22 ` Frank Ch. Eigler
2005-06-16 15:42 ` Doug Evans
2005-06-16 15:49 ` Frank Ch. Eigler
2005-06-16 16:04 ` Doug Evans
2005-06-15 21:39 ` Dave Brolley
2005-06-14 10:25 ` Nick Clifton
2005-06-15 15:40 ` Dave Brolley
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