Hi,

This patch is for cgen generating SID only.

When generating write stacks and the supporting code in order to suppor 
the (delay ...) rtl construct for SID, cgen currently generates a write 
stack for all registers and memory modes regardless of whether they are 
used or not. This is a performance problem uding writeback as the 
majority of the generated stacks are never written to. For most ports 
using (delay ...), the pc and perhaps one or two additional items are 
all that are ever delayed.

This patch keeps track of which hardware and memory modes are actually 
used by (delay ...) and generates only the needed write stacks. One 
potentially icky part of the patch is that it requires that semantics be 
generated first, since this is where the usage information is gathered. 
I modified sid/component/cgen-cpu/CGEN.sh.in to ensure this.

For the internal port for which performance was an issue, this yielded 
an improvement of 17%. I have also tested this on mt and m32r, the two 
other ports currently using write stacks.

Comments? Concerns? OK to commit?

Dave