? sid/bsp/pregen/mep-gdb-tksm.conf ? sid/bsp/pregen/mep-gdb.conf ? sid/bsp/pregen/mep-gloss.conf ? sid/bsp/pregen/mep-little-gdb-tksm.conf ? sid/bsp/pregen/mep-little-gdb.conf ? sid/component/cache/mep-cache.cxx ? sid/component/cache/mep-cache.h ? sid/component/cgen-cpu/mep ? sid/component/families/mep ? sid/component/memory/mep-cache-tag.cxx ? sid/component/memory/mep-cache-tag.h ? sid/component/testsuite/sidcomp.cgen-cpu.mep ? sid/component/testsuite/sidcomp.families.mep ? sid/main/dynamic/mepCfg.cxx ? sid/main/dynamic/mepCfg.h Index: sid/bsp/configrun-sid.in =================================================================== RCS file: /cvs/src/src/sid/bsp/configrun-sid.in,v retrieving revision 1.39 diff -c -p -r1.39 configrun-sid.in *** sid/bsp/configrun-sid.in 18 Oct 2006 18:30:52 -0000 1.39 --- sid/bsp/configrun-sid.in 17 Jan 2007 17:37:09 -0000 *************** require 5.004; *** 17,22 **** --- 17,23 ---- "x86" => "hw-cpu-x86", # INSERT NEW ENTRIES HERE "m32r" => "hw-cpu-m32r/d", + "mep" => "hw-cpu-mep", "mt" => "hw-cpu-mt", "sh5" => "hw-cpu-sh5", "xstormy16" => "hw-cpu-xstormy16", *************** require 5.004; *** 36,41 **** --- 37,43 ---- "x86" => "sw-gloss-generic/libgloss", # INSERT NEW ENTRIES HERE "m32r" => "sw-gloss-m32r/libgloss", + "mep" => "sw-gloss-generic/libgloss", "mt" => "sw-gloss-generic/libgloss", "sh5" => "sw-gloss-generic/libgloss", "xstormy16" => "sw-gloss-generic/libgloss", *************** require 5.004; *** 47,52 **** --- 49,55 ---- "x86" => "0x00000,0x500000", # INSERT NEW ENTRIES HERE "m32r" => "0x00000000,0x00800000", + "mep" => "0x00000000,0x00200000:0x00300000,0x10000", "mt" => "0x00000000,0x00800000", "sh5" => "0x00000000,0x00800000", # check this "xstormy16" => "0x00000000,0x00800000", *************** connect-pin main starting -> init-sequen *** 450,455 **** --- 453,459 ---- connect-pin main stopping -> deinit-sequence input connect-pin init-sequence output-0 -> hw-reset-net input connect-pin hw-reset-net output-0 -> cpu reset! + set target-sched 0-name \"CPU stepping\" connect-pin target-sched 0-event -> cpu step! connect-pin target-sched 0-control <- cpu step-cycles connect-pin target-sched time-query <- cpu time-query *************** connect-pin cpu gprof-pc-hi -> gprof pc- *** 510,517 **** connect-pin cpu cg-caller -> gprof cg-caller connect-pin cpu cg-callee -> gprof cg-callee relate gprof target-component cpu - set gprof bucket-size 4 # bytes per bucket "; } if ($opt_trace_core || $opt_trace_core_visual) --- 514,526 ---- connect-pin cpu cg-caller -> gprof cg-caller connect-pin cpu cg-callee -> gprof cg-callee relate gprof target-component cpu "; + if ($opt_cpu eq "mep") { + $second_section .= "set gprof bucket-size 2\n"; + } + else { + $second_section .= "set gprof bucket-size 4\n"; + } } if ($opt_trace_core || $opt_trace_core_visual) *************** set uart2 sio-framing? 0 *** 713,718 **** --- 722,970 ---- configure_uart1_uart2(); } + elsif ($opt_cpu eq "mep" && ($opt_board ne "gloss-stdio")) + { + # Fallback defaults for incomplete configurations + $mepcfg_index = -1; # flag to detect match + $mepcfg_core_id = 0; + $mepcfg_core_rev = 1; + $mepcfg_imem_size = 0; + $mepcfg_dmem_size = 0; + $mepcfg_icache_size = 0; + $mepcfg_icache_way = 1; + $mepcfg_icache_line_size = 32; + $mepcfg_dcache_size = 0; + $mepcfg_dcache_way = 1; + $mepcfg_dcache_line_size = 32; + $mepcfg_dsu = 0; + $mepcfg_intc_channel_bitw = 32; + $mepcfg_intc = 0; + $mepcfg_dmac = 0; + $mepcfg_cop_vliw_bitw = 0; + $mepcfg_opt_abs = 0; + $mepcfg_opt_ave = 0; + $mepcfg_opt_bit = 0; + $mepcfg_opt_clip = 0; + $mepcfg_opt_cp = 0; + $mepcfg_opt_div = 0; + $mepcfg_opt_ldz = 0; + $mepcfg_opt_min = 0; + $mepcfg_opt_mul = 0; + $mepcfg_opt_sat = 0; + $mepcfg_dsp = 0; + $mepcfg_uci = 0; + @mep_boards = (); + + $mepcfg_index = 1; + $mepcfg_imem_size = 16; + $mepcfg_dmem_size = 32; + $mepcfg_icache_size = 16; + $mepcfg_icache_way = 1; + $mepcfg_icache_line_size = 32; + $mepcfg_dcache_size = 16; + $mepcfg_dcache_way = 1; + $mepcfg_dcache_line_size = 32; + $mepcfg_intc_channel_bitw = 16; + $mepcfg_opt_cp = 1; + $mepcfg_cop_vliw_bitw = 64; + $mepcfg_opt_abs = 1; + $mepcfg_opt_ave = 1; + $mepcfg_opt_bit = 1; + $mepcfg_opt_clp = 1; + $mepcfg_opt_div = 1; + $mepcfg_opt_ldz = 1; + $mepcfg_opt_min = 1; + $mepcfg_opt_mul = 1; + $mepcfg_opt_sat = 1; + $mepcfg_endian = "big"; + $mepcfg_intc = 1; + $mepcfg_dsu = 1; + $mepcfg_dmac = 1; + $mepcfg_dsp = 1; + $mepcfg_uci = 1; + + # Eww, ugly hack to change "hw-cpu-mep" in $first_section to + # "hw-cpu-mep-extNNN" for NNN=$mepcfg_index + $first_section =~ s|new hw-cpu-mep|new hw-cpu-mep-ext$mepcfg_index|; + + # cpu attributes + if ($mepcfg_endian eq "big") { $opt_EB = 1; } + elsif ($mepcfg_endian eq "little") { $opt_EL = 1; } + + $csr17 = (($mepcfg_core_id << 16) | (1 << 8) | $mepcfg_core_rev); + $second_section .= "set cpu csr17 $csr17\n"; + + $second_section .= "set cpu abs-option? " . ($mepcfg_opt_abs) . "\n"; + $second_section .= "set cpu ave-option? " . ($mepcfg_opt_ave) . "\n"; + $second_section .= "set cpu bit-option? " . ($mepcfg_opt_bit) . "\n"; + $second_section .= "set cpu clip-option? " . ($mepcfg_opt_clip) . "\n"; + $second_section .= "set cpu cp-option? " . ($mepcfg_opt_cp) . "\n"; + $second_section .= "set cpu div-option? " . ($mepcfg_opt_div) . "\n"; + $second_section .= "set cpu ldz-option? " . ($mepcfg_opt_ldz) . "\n"; + $second_section .= "set cpu minmax-option? " . ($mepcfg_opt_min) . "\n"; + $second_section .= "set cpu mul-option? " . ($mepcfg_opt_mul) . "\n"; + $second_section .= "set cpu sat-option? " . ($mepcfg_opt_sat) . "\n"; + + $second_section .= "set cpu debug-option? " . ($mepcfg_dsu) . "\n"; + $second_section .= "set cpu dsp-option? " . ($mepcfg_dsp) . "\n"; + $second_section .= "set cpu uci-option? " . ($mepcfg_uci) . "\n"; + + $second_section .= "set cpu vliw32-option? " . ($mepcfg_cop_vliw_bits == 32 ? 1 : 0) . "\n"; + $second_section .= "set cpu vliw64-option? " . ($mepcfg_cop_vliw_bits == 64 ? 1 : 0) . "\n"; + + # dmem/imem calculations; see mep RCFG definition and memory layout chapter + $mep_imem_base = ($mepcfg_imem_size == 0 ? 0 : 0x00200000); + $mep_imem_size = 1024 * $mepcfg_imem_size; + $mep_dmem_base = (($mepcfg_dmem_size == 0) ? 0 : + ($mepcfg_imem_size == 0) ? 0x00200000 : + ($mepcfg_dmem_size > 16) ? 0x00208000 : + ($mepcfg_imem_size >= 12) ? 0x00204000 : + ($mepcfg_dmem_size <= 8) ? 0x00202000 : + ($mepcfg_dmem_size <= 16) ? 0x00204000 : + 0xdeadbeef); # can't happen + + $mep_dmem_bank0_base = $mep_dmem_base; + $mep_dmem_bank1_base = $mep_dmem_base + 1024 * ($mepcfg_dmem_size == 6 ? 4 : + $mepcfg_dmem_size == 12 ? 8 : + $mepcfg_dmem_size == 24 ? 16 : + $mepcfg_dmem_size / 2); + $mep_dmem_bank0_size = 1024 * $mepcfg_dmem_size / 2; + $mep_dmem_bank1_size = 1024 * $mepcfg_dmem_size / 2; + + # These are complex bitfields: + # LCFG: local memory configuration + $csr27 = (0x01000100 | # fixed bits + ($mepcfg_imem_size << 16) | # IRSZ + ($mepcfg_dmem_size << 0) | # DRSZ + (($mep_dmem_base >> 12) & 0xf)); # DRBA + $second_section .= "set cpu csr27 $csr27\n"; + + # CCFG: cache memory configuration + $csr28 = (0x00000000 | # no fixed bits + ($mepcfg_icache_size << 16) | # ICSZ + ($mepcfg_dcache_size << 0)); # DCSZ + $second_section .= "set cpu csr28 $csr28\n"; + + # control bus layout + $zeroth_section .= "load libmepfamily.la mepfamily_component_library\n"; + $first_section .= "# control space + new hw-mapper-basic cpu-control-space + set cpu-control-space latency 1 + new hw-mapper-basic cpu-local-space + " . + ($mepcfg_dsu ? "new hw-debug-mep cpu-dsu\n" : "") . + ($mepcfg_dmac ? "new hw-dma-mep cpu-dmac\n" : "") . + ($mepcfg_intc ? "new hw-interrupt-mep-${mepcfg_intc_channel_bitw} cpu-intc\n" : ""); + + $second_section .= "# configuration / connection of control space peripherals + connect-bus cpu control-space cpu-control-space access-port + " . + ($mepcfg_dsu ? "connect-bus cpu-control-space dsu[4*0x800-0x802] cpu-dsu status-regs + connect-bus cpu-control-space dsu[4*0x900-0x902] cpu-dsu insn-regs + connect-bus cpu-control-space dsu[4*0xA00-0xA05] cpu-dsu data-regs\n" : "") . + ($mepcfg_dmac ? "connect-bus cpu-control-space dmac[4*0x1000-0x1009] cpu-dmac control-regs-low + connect-bus cpu-control-space dmac[4*0x1FFF-0x1FFF] cpu-dmac control-regs-high\n" : "") . + ($mepcfg_intc ? "connect-bus cpu-control-space intc[4*0x0-0x7] cpu-intc registers\n" : ""); + + $third_section .= + ($mepcfg_dmac ? "# mep dmac connection + connect-bus cpu-dmac local-memory cpu-local-space access-port + connect-bus cpu-dmac main-memory cpu-mapper access-port + set target-sched 2-name \"DMA controller burst events\" + connect-pin target-sched 2-event -> cpu-dmac burst-event + connect-pin target-sched 2-control <- cpu-dmac burst-control + " : "") . + ($mepcfg_intc ? "# mep intc connection + connect-pin cpu-intc interrupt -> cpu interrupt + " : ""); + + # mep instruction fetch buffer: 8 bytes + $first_section .= "# instruction fetch buffer + new hw-cache-buffer-8 cpu-insn-buffer + set cpu-insn-buffer write-through? true + connect-pin cache-flush-net output-0 -> cpu-insn-buffer flush-all + connect-pin init-sequence output-1 -> cpu-insn-buffer invalidate-all + "; + + # "default" memory layout + push @opt_memory_region, "0x00000000,0x200,latency=5"; # vec + push @opt_memory_region, "0x00010000,0x60000,latency=5"; # romdata.m + push @opt_memory_region, "0x00080000,0x80000,latency=5"; # code.m + push @opt_memory_region, "0x00100000,0x80000,latency=5"; # data.m + # push @opt_memory_region, "0x00300000,0x10000"; # icache data testing area + # push @opt_memory_region, "0x00310000,0x10000"; # icache tag testing area + # push @opt_memory_region, "0x00320000,0x10000"; # dcache data testing area + # push @opt_memory_region, "0x00330000,0x10000"; # dcache tag testing area + push @opt_memory_region, "0x01000000,0x8000,latency=5"; # romdata.s + push @opt_memory_region, "0x01008000,0x8000,latency=5"; # data.s + push @opt_memory_region, "0x02000000,0x100000,latency=5"; # data.l + push @opt_memory_region, "0x02200000,0x100000,latency=5"; # romdata.l + push @opt_memory_region, "0x02300000,0x100000,latency=5"; # code.l + push @opt_memory_region, "0x03000000,0x100000,latency=5"; # stack + push @opt_memory_region, "0x04000000,0x100000,latency=5"; # heap + + $third_section .= "connect-bus cpu-mapper local:[0x00200000,0x00210000] cpu-local-space access-port\n"; + + push @opt_memory_region, ($mep_imem_base - 0x00200000) . "," . $mep_imem_size . ",bus=cpu-local-space,latency=2" if $mep_imem_size; + push @opt_memory_region, ($mep_dmem_bank0_base - 0x00200000) . "," . $mep_dmem_bank0_size . ",bus=cpu-local-space,latency=2" if $mep_dmem_bank0_size; + push @opt_memory_region, ($mep_dmem_bank1_base - 0x00200000) . "," . $mep_dmem_bank1_size . ",bus=cpu-local-space,latency=2" if $mep_dmem_bank1_size; + + if ($mepcfg_icache_size) + { + $cachetype = + ($mepcfg_icache_way == 1 ? "direct" : ($mepcfg_icache_way . "way")) . "/" . + $mepcfg_icache_size . "kb" . "/" . + $mepcfg_icache_line_size . + ($mepcfg_icache_way == 1 ? "" : "/random"); + + configure_mep_cached_bus("insn", $cachetype, $mepcfg_dsu); + $third_section .= "# icache tag test area + new hw-glue-probe-bus cpu-insn-cache-tagtest + new hw-memory-ram/rom-basic cpu-insn-cache-tag + set cpu-insn-cache-tag size 0x10000 + connect-bus cpu-mapper [0x00310000-0x0031FFFF] cpu-insn-cache-tagtest upstream + connect-bus cpu-insn-cache-tagtest downstream cpu-insn-cache-tag read-write-port + connect-pin cpu-insn-cache-tagtest address -> cpu-insn-cache invalidate-all + "; + } + else + { + $second_section .= " + disconnect-bus cpu insn-memory cpu-mapper access-port + connect-bus cpu insn-memory cpu-insn-buffer upstream + connect-bus cpu-insn-buffer downstream cpu-mapper access-port + connect-pin init-sequence output-0 -> cpu-insn-buffer invalidate-all\n"; + } + if ($mepcfg_dcache_size) + { + $cachetype = + ($mepcfg_dcache_way == 1 ? "direct" : ($mepcfg_dcache_way . "way")) . "/" . + $mepcfg_dcache_size . "kb" . "/" . + $mepcfg_dcache_line_size . + ($mepcfg_dcache_way == 1 ? "" : "/random"); + configure_mep_cached_bus("data", $cachetype, $mepcfg_dsu); + $bus_upstream = "cpu-data-cachefilter access-port"; + $third_section .= "# dcache tag test area + new hw-glue-probe-bus cpu-data-cache-tagtest + new hw-memory-ram/rom-basic cpu-data-cache-tag + set cpu-data-cache-tag size 0x10000 + connect-bus cpu-mapper [0x00330000-0x0033FFFF] cpu-data-cache-tagtest upstream + connect-bus cpu-data-cache-tagtest downstream cpu-data-cache-tag read-write-port + connect-pin cpu-data-cache-tagtest address -> cpu-data-cache invalidate-all + "; + } + else + { + $bus_upstream = "cpu-mapper access-port"; + } + + if ($opt_board =~ /gloss/) + { + # prevent configure_gloss from adding in the overlapping defaults + $gloss_memspecs{$opt_cpu}=""; + configure_gloss ($opt_board); + } + } elsif ($opt_board =~ /gloss/) { configure_gloss($opt_board); *************** connect-bus gloss target-memory data-map *** 903,910 **** --- 1155,1207 ---- } + sub configure_mep_cached_bus + { + my $addrspace = $_[0]; + my $cachetype = $_[1]; + my $dsu_p = $_[2]; + + $first_section .= "# $addrspace caching + new hw-mapper-transparent cpu-${addrspace}-cachefilter + new hw-cache-$cachetype cpu-${addrspace}-cache + set cpu-${addrspace}-cache hit-latency 1 + set cpu-${addrspace}-cache miss-latency 1 + connect-pin cpu ${addrspace}-cache-enable -> cpu-${addrspace}-cachefilter bank + connect-pin cache-flush-net output-0 -> cpu-${addrspace}-cache flush-all + connect-pin cache-flush-net output-1 -> cpu-${addrspace}-cache invalidate-all + "; + $second_section .= "# $addrspace cache filtering + disconnect-bus cpu ${addrspace}-memory $bus_upstream + "; + + if ($addrspace eq "insn") { + $second_section .= "connect-bus cpu insn-memory cpu-insn-buffer upstream\n"; + $cpubus = "cpu-insn-buffer downstream"; + } else { + $cpubus = "cpu data-memory"; + } + if ($dsu_p) { + $second_section .= "connect-bus $cpubus cpu-dsu ${addrspace}-upstream + connect-bus cpu-dsu ${addrspace}-downstream cpu-${addrspace}-cachefilter access-port + "; + } else { + $second_section .= "connect-bus $cpubus cpu-${addrspace}-cachefilter access-port\n"; + } + $second_section .= + "connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00000000-0x007FFFFF]{0,1}:uncacheable cpu-mapper access-port + connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00800000-0x7FFFFFFF]{1}:cached cpu-${addrspace}-cache upstream + connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x00800000-0x7FFFFFFF]{0}:uncached cpu-mapper access-port + connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0x80000000-0xBFFFFFFF]{0,1}:uncacheable cpu-mapper access-port + connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0xC0000000-0xFFFFFFFF]{1}:cached cpu-${addrspace}-cache upstream + connect-bus cpu-${addrspace}-cachefilter ${addrspace}:[0xC0000000-0xFFFFFFFF]{0}:uncached cpu-mapper access-port + connect-bus cpu-${addrspace}-cache downstream cpu-mapper access-port + # $addrspace cache setup + set cpu-${addrspace}-cache report-heading \"${addrspace} profile report\" + connect-pin init-sequence output-1 -> cpu-${addrspace}-cache invalidate-all\n" . + ($opt_trace_counter ? "connect-pin deinit-sequence output-6 -> cpu-${addrspace}-cache report!\n" : ""); + } if ($opt_cpu eq "arm") { *************** if ($opt_cpu eq "xstormy16") *** 926,931 **** --- 1223,1232 ---- $enable_z_packet = "true"; } + if ($opt_cpu eq "mep") + { + $enable_z_packet = "true"; + } # --engine if ($opt_engine eq "pbb") Index: sid/bsp/pregen/pregen-configs.in =================================================================== RCS file: /cvs/src/src/sid/bsp/pregen/pregen-configs.in,v retrieving revision 1.11 diff -c -p -r1.11 pregen-configs.in *** sid/bsp/pregen/pregen-configs.in 18 Oct 2006 18:30:52 -0000 1.11 --- sid/bsp/pregen/pregen-configs.in 11 Jan 2007 19:10:24 -0000 *************** mvic a.out.conf i386-gloss.conf *** 72,77 **** --- 72,92 ---- crs --cpu=x86 --no-run --gdb=5000 mvic sid.conf i386-gdb.conf + crs --cpu=mep --no-run a.out + mvic a.out.conf mep-gloss.conf + + crs --cpu=mep --no-run --gdb=5000 -EB + mvic sid.conf mep-gdb.conf + + crs --cpu=mep --no-run --gdb=5000 -EB --tksm + mvic sid.conf mep-gdb-tksm.conf + + crs --cpu=mep --no-run --gdb=5000 -EL + mvic sid.conf mep-little-gdb.conf + + crs --cpu=mep --no-run --gdb=5000 -EL --tksm + mvic sid.conf mep-little-gdb-tksm.conf + crs --cpu=mt --no-run a.out mvic a.out.conf mt-gloss.conf Index: sid/component/CATALOG =================================================================== RCS file: /cvs/src/src/sid/component/CATALOG,v retrieving revision 1.18 diff -c -p -r1.18 CATALOG *** sid/component/CATALOG 18 Oct 2006 18:38:24 -0000 1.18 --- sid/component/CATALOG 11 Jan 2007 19:10:24 -0000 *************** lcd liblcd-char-display.la *** 19,24 **** --- 19,25 ---- loader libloader.la loader_component_library Red Hat mapper libmapper.la mapper_component_library Red Hat memory libmemory.la mem_component_library Red Hat + mepfamily libmepfamily.la mepfamily_component_library Red Hat mmu libmmu.la mmu_component_library Red Hat parport libparport.la parport_component_library Red Hat profiling libprof.la prof_component_library Red Hat *************** hw-cache-* Other memory caches (ref. co *** 42,47 **** --- 43,49 ---- hw-cpu-arm7t ARM7 / ARM7T CPU model hw-cpu-x86 X86 CPU model hw-cpu-m32r/d M32R/D CPU model + hw-cpu-mep Toshiba Media Processor (MeP) CPU model hw-cpu-sh2 SH2 CPU model hw-cpu-sh2e SH2e CPU model hw-cpu-sh2a-nofpu SH2a CPU model no fpu *************** hw-cpu-sh5-compact SH5 CPU model compa *** 60,67 **** --- 62,71 ---- hw-cpu-sh5-32media SH5 CPU model 32 bit compact and media ISAs hw-cpu-sh5-64media SH5 CPU model 64 bit compact and media ISAs hw-cpu-xstormy16 Sanyo Xstormy16 CPU model + hw-debug-mep Toshiba MeP debug support unit (DSU) hw-disk-harddrive Newer IDE hard drive model (controller + drives) hw-disk-ide IDE hard drive model (controller + drives) + hw-dma-mep Toshiba MeP DMA controller hw-glue-bus-mux Bus multiplexer hw-glue-pin-pacer Pin signal FIFO queue. hw-glue-probe-bus Bus traffic tracer *************** hw-glue-sequence Sequential pin e *** 69,74 **** --- 73,79 ---- hw-input-keyboard PC keyboard model hw-interrupt-arm/ref ARM7 reference peripheral: interrupt controller hw-interrupt-cogent/cma222 Interrupt controller: Cogent CMA222 ARM CPU board + hw-interrupt-mep Toshiba MeP interrupt controller unit hw-lcd-hd44780u HD44780U LCD controller hw-lcd-char-display curses based LCD display hw-mapper-basic Generic address space decoder/mapper Index: sid/component/tconfig.in =================================================================== RCS file: /cvs/src/src/sid/component/tconfig.in,v retrieving revision 1.6 diff -c -p -r1.6 tconfig.in *** sid/component/tconfig.in 18 Oct 2006 18:38:24 -0000 1.6 --- sid/component/tconfig.in 11 Jan 2007 19:10:25 -0000 *************** *** 6,11 **** --- 6,12 ---- #define SIDTARGET_MIPS @sidtarget_mips@ #define SIDTARGET_M32R @sidtarget_m32r@ #define SIDTARGET_M68K @sidtarget_m68k@ + #define SIDTARGET_MEP @sidtarget_mep@ #define SIDTARGET_MT @sidtarget_mt@ #define SIDTARGET_PPC @sidtarget_ppc@ #define SIDTARGET_SH @sidtarget_sh@ Index: sid/component/bochs/config.sub =================================================================== RCS file: /cvs/src/src/sid/component/bochs/config.sub,v retrieving revision 1.1 diff -c -p -r1.1 config.sub *** sid/component/bochs/config.sub 27 Nov 2001 22:59:00 -0000 1.1 --- sid/component/bochs/config.sub 11 Jan 2007 19:10:25 -0000 *************** case $basic_machine in *** 180,186 **** | alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \ | alphaev6[78] \ | we32k | ns16k | clipper | i370 | sh | powerpc | powerpcle \ ! | 1750a | dsp16xx | pdp11 | mips16 | mips64 | mipsel | mips64el \ | mips64orion | mips64orionel | mipstx39 | mipstx39el \ | mips64vr4300 | mips64vr4300el | mips64vr4100 | mips64vr4100el \ | mips64vr5000 | miprs64vr5000el | mcore \ --- 180,187 ---- | alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \ | alphaev6[78] \ | we32k | ns16k | clipper | i370 | sh | powerpc | powerpcle \ ! | 1750a | dsp16xx | pdp11 | mep \ ! | mips16 | mips64 | mipsel | mips64el \ | mips64orion | mips64orionel | mipstx39 | mipstx39el \ | mips64vr4300 | mips64vr4300el | mips64vr4100 | mips64vr4100el \ | mips64vr5000 | miprs64vr5000el | mcore \ *************** case $basic_machine in *** 223,229 **** | mipstx39-* | mipstx39el-* | mcore-* \ | f301-* | armv*-* | s390-* | sv1-* | t3e-* \ | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \ ! | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \ | bs2000-*) ;; # Recognize the various machine names and aliases which stand --- 224,230 ---- | mipstx39-* | mipstx39el-* | mcore-* \ | f301-* | armv*-* | s390-* | sv1-* | t3e-* \ | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \ ! | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* | mep-* \ | bs2000-*) ;; # Recognize the various machine names and aliases which stand Index: sid/component/cache/Makefile.am =================================================================== RCS file: /cvs/src/src/sid/component/cache/Makefile.am,v retrieving revision 1.5 diff -c -p -r1.5 Makefile.am *** sid/component/cache/Makefile.am 10 May 2005 15:41:05 -0000 1.5 --- sid/component/cache/Makefile.am 11 Jan 2007 19:10:26 -0000 *************** AM_CXXFLAGS=$(TOP_CXXFLAGS) *** 8,14 **** AM_MAKEFLAGS= "TOP_CXXFLAGS=$(TOP_CXXFLAGS)" INCLUDES = -I. -I../../include -I$(srcdir)/../../include ! EXTRA_SOURCES= libcache_la_SOURCES = cache.cxx cache.h \ $(EXTRA_SOURCES) \ cacheutil.cxx cacheutil.h log2.h --- 8,14 ---- AM_MAKEFLAGS= "TOP_CXXFLAGS=$(TOP_CXXFLAGS)" INCLUDES = -I. -I../../include -I$(srcdir)/../../include ! EXTRA_SOURCES=mep-cache.cxx mep-cache.h libcache_la_SOURCES = cache.cxx cache.h \ $(EXTRA_SOURCES) \ cacheutil.cxx cacheutil.h log2.h Index: sid/component/cache/cache.cxx =================================================================== RCS file: /cvs/src/src/sid/component/cache/cache.cxx,v retrieving revision 1.22 diff -c -p -r1.22 cache.cxx *** sid/component/cache/cache.cxx 10 May 2006 20:24:48 -0000 1.22 --- sid/component/cache/cache.cxx 11 Jan 2007 19:10:26 -0000 *************** using std::cout; *** 25,30 **** --- 25,31 ---- using std::endl; #include "cache.h" + #include "mep-cache.h" static string buffer_sizes[] = { "4", "8" }; *************** static cache_replacement_lru lru_replace *** 47,52 **** --- 48,54 ---- static cache_replacement_fifo fifo_replacement; static cache_replacement_random random_replacement; static cache_line_factory internal_line_factory; + static mep_assoc_replacement_algorithm mep_assoc_replacement; cache_component::cache_component (unsigned assocy, unsigned cache_sz, *************** CacheListTypes () *** 1087,1095 **** --- 1089,1170 ---- types.push_back ("hw-blocking-cache-" + type); } } + + for (unsigned i = 0; i < (sizeof (assocs) / sizeof (string)); i++) + for (unsigned j = 0; j < (sizeof (cache_sizes) / sizeof (string)); j++) + for (unsigned k = 0; k < (sizeof (line_sizes) / sizeof (string)); k++) + { + type = "hw-mep-cache-"; + type += assocs[i] + "/"; + type += cache_sizes[j] + "kb/"; + type += line_sizes[k]; + types.push_back (type); + } + return types; } + static component * + create_mep_cache (vector& parts) + { + // decode cache types: hw-mep-cache-/kb/ + // + string assoc_string = parts[3]; + + bool match; + int i; + for (match = false, i = 0; i < sizeof (assocs) / sizeof (string); i++) + if (assoc_string == assocs[i]) + match = true; + + if (!match) + return 0; + + // Parse "kb", where is a positive integer. + int cache_sz; + string cache_size_string = parts[4].substr (0, parts[4].length() - 2); + for (match = false, i = 0; i < sizeof (cache_sizes) / sizeof (string); i++) + if (cache_size_string == cache_sizes[i]) + { + cache_sz = atoi (cache_size_string.c_str ()) * 1024; + match = true; + } + + if (!match) + return 0; + + int line_sz; + string line_size_string = parts[5]; + for (match = false, i = 0; i < sizeof (line_sizes) / sizeof (string); i++) + if (line_size_string == line_sizes[i]) + { + line_sz = atoi (line_size_string.c_str ()); + match = true; + } + + if (!match) + return 0; + + int assoc; + if (assoc_string == "direct") + assoc = 1; + else + { + int pos; + if ((pos = assoc_string.find ("way", 0)) == string::npos) + return 0; + + assoc_string.erase (pos, assoc_string.length () - pos); + if ((assoc = atoi (assoc_string.c_str ())) == 0) + return 0; + } + + if (assoc == 1) + return new mep_cache (assoc, cache_sz, line_sz, null_replacement); + + return new mep_cache (assoc, cache_sz, line_sz, mep_assoc_replacement); + } + static component* CacheCreate (const string& typeName) { *************** CacheCreate (const string& typeName) *** 1120,1125 **** --- 1195,1203 ---- vector parts = sidutil::tokenize (typeName, "-/"); + if (parts.size () >= 6 && parts[0] == "hw" && parts[1] == "mep" && parts[1] != "cache") + return create_mep_cache (parts); + unsigned extra_ix; if (parts.size () >= 5 && parts[0] == "hw" && parts[1] == "cache") extra_ix = 0; Index: sid/component/cgen-cpu/compCGEN.cxx =================================================================== RCS file: /cvs/src/src/sid/component/cgen-cpu/compCGEN.cxx,v retrieving revision 1.21 diff -c -p -r1.21 compCGEN.cxx *** sid/component/cgen-cpu/compCGEN.cxx 23 Oct 2006 21:11:51 -0000 1.21 --- sid/component/cgen-cpu/compCGEN.cxx 11 Jan 2007 19:10:27 -0000 *************** extern "C" { *** 26,31 **** --- 26,38 ---- #if SIDTARGET_M32R #include "m32rbf.h" #endif + #if SIDTARGET_MEP + #include "mep_basic.h" + // begin-mep-includes + #include "mep_ext1.h" + #include "mep_ext2.h" + // end-mep-includes + #endif #if SIDTARGET_MT #include "mt.h" #endif *************** compCGENListTypes () *** 320,325 **** --- 327,339 ---- #if SIDTARGET_ARM types.push_back ("hw-cpu-arm7t"); #endif + #if SIDTARGET_MEP + types.push_back ("hw-cpu-mep"); + // begin-mep-types + types.push_back ("hw-cpu-mep-ext1"); + types.push_back ("hw-cpu-mep-ext2"); + // end-mep-types + #endif #if SIDTARGET_MT types.push_back ("hw-cpu-mt"); #endif *************** compCGENCreate (const string& typeName) *** 363,368 **** --- 377,392 ---- if (typeName == "hw-cpu-arm7t") return new arm7f::arm7f_cpu (); #endif + #if SIDTARGET_MEP + if (typeName == "hw-cpu-mep") + return new mep_basic::mep_basic_cpu (); + // begin-mep-constructors + if (typeName == "hw-cpu-mep-ext1") + return new mep_ext1::mep_ext1_cpu (); + if (typeName == "hw-cpu-mep-ext2") + return new mep_ext2::mep_ext2_cpu (); + // end-mep-constructors + #endif #if SIDTARGET_MT if (typeName == "hw-cpu-mt") return new mt::mt_cpu (); Index: sid/component/cgen-cpu/configure.in =================================================================== RCS file: /cvs/src/src/sid/component/cgen-cpu/configure.in,v retrieving revision 1.11 diff -c -p -r1.11 configure.in *** sid/component/cgen-cpu/configure.in 18 Oct 2006 18:37:51 -0000 1.11 --- sid/component/cgen-cpu/configure.in 11 Jan 2007 19:10:28 -0000 *************** if test $sidtarget_m32r -eq 1; then *** 53,58 **** --- 53,62 ---- cpu_subdirs="$cpu_subdirs m32r" AC_CONFIG_SUBDIRS(m32r) fi + if test $sidtarget_mep -eq 1; then + cpu_subdirs="$cpu_subdirs mep" + AC_CONFIG_SUBDIRS(mep) + fi if test $sidtarget_mt -eq 1; then cpu_subdirs="$cpu_subdirs mt" AC_CONFIG_SUBDIRS(mt) Index: sid/component/families/configure.in =================================================================== RCS file: /cvs/src/src/sid/component/families/configure.in,v retrieving revision 1.2 diff -c -p -r1.2 configure.in *** sid/component/families/configure.in 4 Jun 2005 03:23:07 -0000 1.2 --- sid/component/families/configure.in 11 Jan 2007 19:10:30 -0000 *************** CY_SIDTARGET_CHECK *** 20,25 **** --- 20,29 ---- # to the list. family_subdirs= + if test $sidtarget_mep -eq 1; then + family_subdirs="$family_subdirs mep" + AC_CONFIG_SUBDIRS(mep) + fi AC_SUBST(family_subdirs) AC_OUTPUT([Makefile]) Index: sid/component/memory/Makefile.am =================================================================== RCS file: /cvs/src/src/sid/component/memory/Makefile.am,v retrieving revision 1.3 diff -c -p -r1.3 Makefile.am *** sid/component/memory/Makefile.am 4 Aug 2001 11:34:52 -0000 1.3 --- sid/component/memory/Makefile.am 17 Jan 2007 21:36:35 -0000 *************** pkglib_LTLIBRARIES = libmemory.la *** 7,12 **** --- 7,13 ---- INCLUDES = -I. -I../../include -I$(srcdir)/../../include noinst_HEADERS = generic.h ramrom.h flash.h at29.h libmemory_la_SOURCES = components.cxx generic.cxx ramrom.cxx flash.cxx \ + mep-cache-tag.cxx \ at29.cxx am29.cxx libmemory_la_LDFLAGS = -module -no-undefined Index: sid/component/memory/components.cxx =================================================================== RCS file: /cvs/src/src/sid/component/memory/components.cxx,v retrieving revision 1.2 diff -c -p -r1.2 components.cxx *** sid/component/memory/components.cxx 1 Mar 2006 21:07:01 -0000 1.2 --- sid/component/memory/components.cxx 17 Jan 2007 21:36:35 -0000 *************** *** 15,20 **** --- 15,21 ---- #include "am29.h" #include "at29.h" #include "ramrom.h" + #include "mep-cache-tag.h" using std::vector; using std::string; *************** compMemoryListTypes() *** 52,57 **** --- 53,60 ---- types.push_back(string("hw-memory-flash-am29") + ft->name); } + types.push_back ("hw-mep-cache-tag-memory"); + return types; } *************** compMemoryCreate(const string& typeName) *** 90,95 **** --- 93,101 ---- if (that_type == typeName) return new am29_flash_memory(ft->memory_size, ft->sector_size, ft->device_id); } + + if (typeName == "hw-mep-cache-tag-memory") + return new mep_cache_tag_memory (); } catch (...) { } Index: sid/component/memory/generic.cxx =================================================================== RCS file: /cvs/src/src/sid/component/memory/generic.cxx,v retrieving revision 1.8 diff -c -p -r1.8 generic.cxx *** sid/component/memory/generic.cxx 10 Jun 2003 18:27:10 -0000 1.8 --- sid/component/memory/generic.cxx 17 Jan 2007 21:36:35 -0000 *************** *** 1,6 **** // generic.cxx - a class of generic memories. -*- C++ -*- ! // Copyright (C) 1999-2001,2003 Red Hat. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. --- 1,6 ---- // generic.cxx - a class of generic memories. -*- C++ -*- ! // Copyright (C) 1999-2001, 2003, 2007 Red Hat. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. *************** generic_memory::generic_memory() throw ( *** 55,61 **** imagemmap_pin (this, & generic_memory::imagemmap_handler), imagemsync_pin (this, & generic_memory::imagemsync_handler), read_latency (0), ! write_latency (0) { this->max_buffer_length = 32UL * 1024UL * 1024UL; this->buffer = 0; --- 55,64 ---- imagemmap_pin (this, & generic_memory::imagemmap_handler), imagemsync_pin (this, & generic_memory::imagemsync_handler), read_latency (0), ! write_latency (0), ! base_address (0), ! warn_rom_write (false), ! allow_rom_write (false) { this->max_buffer_length = 32UL * 1024UL * 1024UL; this->buffer = 0; *************** generic_memory::generic_memory() throw ( *** 82,87 **** --- 85,98 ---- add_attribute ("read-latency", & this->read_latency, "setting"); add_attribute ("write-latency", & this->write_latency, "setting"); + add_attribute ("base-address", & this->base_address, "setting"); + + add_attribute ("warn-rom-write-option?", & this->warn_rom_write, "setting"); + add_attribute ("allow-rom-write-option?", & this->allow_rom_write, "setting"); + + // Undocumented, dangerous, do not use ... + add_attribute_ro ("buffer-base-UNSAFE", (host_int_4*) & this->buffer); + add_attribute_ro ("buffer-length-UNSAFE", & this->buffer_length); add_attribute_virtual ("state-snapshot", this, & generic_memory::save_state, *************** generic_memory::generic_memory() throw ( *** 89,95 **** } ! generic_memory::~generic_memory () throw() { assert (this->buffer); if (this->mmapping_p) --- 100,106 ---- } ! generic_memory::~generic_memory () { assert (this->buffer); if (this->mmapping_p) Index: sid/component/memory/generic.h =================================================================== RCS file: /cvs/src/src/sid/component/memory/generic.h,v retrieving revision 1.5 diff -c -p -r1.5 generic.h *** sid/component/memory/generic.h 3 Aug 2001 06:02:46 -0000 1.5 --- sid/component/memory/generic.h 17 Jan 2007 21:36:35 -0000 *************** *** 1,6 **** // generic.h - Header for the generic_memory class. -*- C++ -*- ! // Copyright (C) 1999-2001 Red Hat. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. --- 1,6 ---- // generic.h - Header for the generic_memory class. -*- C++ -*- ! // Copyright (C) 1999-2001, 2007 Red Hat. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. *************** class generic_memory: public virtual com *** 69,75 **** { public: generic_memory() throw (bad_alloc); ! ~generic_memory() throw (); protected: // memory buffers --- 69,75 ---- { public: generic_memory() throw (bad_alloc); ! ~generic_memory(); protected: // memory buffers *************** protected: *** 94,106 **** host_int_4 max_buffer_length; bool attempt_resize (host_int_4 new_length) throw(); private: string get_size_attr (); component::status set_size_attr (const string& s); - host_int_2 read_latency; - host_int_2 write_latency; - string image_file_name; callback_pin imageload_pin; void imageload_handler (host_int_4); --- 94,110 ---- host_int_4 max_buffer_length; bool attempt_resize (host_int_4 new_length) throw(); + host_int_4 base_address; + bool warn_rom_write; + bool allow_rom_write; + + host_int_2 read_latency; + host_int_2 write_latency; + private: string get_size_attr (); component::status set_size_attr (const string& s); string image_file_name; callback_pin imageload_pin; void imageload_handler (host_int_4); *************** public: *** 125,131 **** // some macros to make manufacturing of the cartesian-product calls simpler #define SID_GB_WRITE(type2) \ bus::status write(host_int_4 address, type2 data) throw () \ ! { return bus::unpermitted; } #define SID_GB_READ(type2) \ bus::status read(host_int_4 address, type2& data) throw () \ --- 129,141 ---- // some macros to make manufacturing of the cartesian-product calls simpler #define SID_GB_WRITE(type2) \ bus::status write(host_int_4 address, type2 data) throw () \ ! { if (! target->warn_rom_write && ! target->allow_rom_write) \ ! return bus::unpermitted; \ ! cerr << "Warning: invalid write to ROM address 0x" << std::hex << target->base_address + address << endl; \ ! if (target->allow_rom_write) \ ! return this->write_any(address,data); \ ! else \ ! return bus::ok; } #define SID_GB_READ(type2) \ bus::status read(host_int_4 address, type2& data) throw () \ *************** protected: *** 160,165 **** --- 170,179 ---- template inline bus::status read_any(host_int_4 address, DataType& data); + + template + inline bus::status + write_any(host_int_4 address, DataType data); }; *************** public: *** 190,200 **** SID_GB_WRITE(big_int_8); #undef SID_GB_WRITE - - protected: - template - inline bus::status - write_any(host_int_4 address, DataType data); }; --- 204,209 ---- *************** protected: *** 203,209 **** template inline bus::status ! generic_read_write_bus::write_any(host_int_4 address, DataType data) { const unsigned width = sizeof(typename DataType::value_type); --- 212,218 ---- template inline bus::status ! generic_read_only_bus::write_any(host_int_4 address, DataType data) { const unsigned width = sizeof(typename DataType::value_type); Index: sid/component/testsuite/sidcomp.cgen-cpu/cpudocs.exp =================================================================== RCS file: /cvs/src/src/sid/component/testsuite/sidcomp.cgen-cpu/cpudocs.exp,v retrieving revision 1.2 diff -c -p -r1.2 cpudocs.exp *** sid/component/testsuite/sidcomp.cgen-cpu/cpudocs.exp 4 Aug 2001 12:10:32 -0000 1.2 --- sid/component/testsuite/sidcomp.cgen-cpu/cpudocs.exp 11 Jan 2007 19:10:31 -0000 *************** load_lib "docs.exp" *** 2,4 **** --- 2,5 ---- doc_test cgen-cpu/arm7t hw-cpu-arm7t doc_test cgen-cpu/m32r hw-cpu-m32r/d + doc_test cgen-cpu/mep hw-cpu-mep Index: sid/component/testsuite/sidcomp.cgen-cpu/cpumonkey.exp =================================================================== RCS file: /cvs/src/src/sid/component/testsuite/sidcomp.cgen-cpu/cpumonkey.exp,v retrieving revision 1.2 diff -c -p -r1.2 cpumonkey.exp *** sid/component/testsuite/sidcomp.cgen-cpu/cpumonkey.exp 4 Apr 2001 04:19:23 -0000 1.2 --- sid/component/testsuite/sidcomp.cgen-cpu/cpumonkey.exp 11 Jan 2007 19:10:31 -0000 *************** proc pin_safe_p {pin_name} { *** 36,38 **** --- 36,41 ---- return 1 } + if {$sidtarget(mep)} then { + monkey_test hw-cpu-mep cgen_component_library libcgencpu.la 3m + } else { untested "hw-cpu-mep not available" } Index: sid/config/config.sub =================================================================== RCS file: /cvs/src/src/sid/config/config.sub,v retrieving revision 1.7 diff -c -p -r1.7 config.sub *** sid/config/config.sub 16 Dec 2005 10:23:16 -0000 1.7 --- sid/config/config.sub 11 Jan 2007 19:10:33 -0000 *************** case $basic_machine in *** 240,245 **** --- 240,246 ---- | i370 | i860 | i960 | ia64 \ | ip2k | iq2000 \ | m32r | m32rle | m68000 | m68k | m88k | maxq | mcore \ + | mep \ | mips | mipsbe | mipseb | mipsel | mipsle \ | mips16 \ | mips64 | mips64el \ *************** case $basic_machine in *** 318,323 **** --- 319,325 ---- | m32r-* | m32rle-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | maxq-* | mcore-* \ + | mep-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ Index: sid/config/info.tcl.in =================================================================== RCS file: /cvs/src/src/sid/config/info.tcl.in,v retrieving revision 1.8 diff -c -p -r1.8 info.tcl.in *** sid/config/info.tcl.in 18 Oct 2006 18:42:36 -0000 1.8 --- sid/config/info.tcl.in 11 Jan 2007 19:10:33 -0000 *************** set sidtarget(x86) @sidtarget_x86@ *** 18,23 **** --- 18,24 ---- set sidtarget(mips) @sidtarget_mips@ set sidtarget(m32r) @sidtarget_m32r@ set sidtarget(m68k) @sidtarget_m68k@ + set sidtarget(mep) @sidtarget_mep@ set sidtarget(mt) @sidtarget_mt@ set sidtarget(ppc) @sidtarget_ppc@ set sidtarget(sh) @sidtarget_sh@ Index: sid/config/sidtargets.m4 =================================================================== RCS file: /cvs/src/src/sid/config/sidtargets.m4,v retrieving revision 1.10 diff -c -p -r1.10 sidtargets.m4 *** sid/config/sidtargets.m4 30 Nov 2006 18:48:07 -0000 1.10 --- sid/config/sidtargets.m4 11 Jan 2007 19:10:33 -0000 *************** sidtarget_x86=$sidtarget_default *** 41,46 **** --- 41,47 ---- sidtarget_mips=$sidtarget_default sidtarget_m32r=$sidtarget_default sidtarget_m68k=$sidtarget_default + sidtarget_mep=$sidtarget_default sidtarget_mt=$sidtarget_default sidtarget_ppc=$sidtarget_default sidtarget_sh=$sidtarget_default *************** do *** 57,62 **** --- 58,64 ---- mips*) sidtarget_mips=1 ;; m32r*) sidtarget_m32r=1 ;; m68k*) sidtarget_m68k=1 ;; + mep*) sidtarget_mep=1 ;; mt*) sidtarget_mt=1 ;; powerpc*) sidtarget_ppc=1 ;; ppc*) sidtarget_ppc=1 ;; *************** case 1 in *** 74,79 **** --- 76,82 ---- ${sidtarget_mips}) ;; ${sidtarget_m32r}) ;; ${sidtarget_m68k}) ;; + ${sidtarget_mep}) ;; ${sidtarget_mt}) ;; ${sidtarget_ppc}) ;; ${sidtarget_sh}) ;; *************** AC_SUBST(sidtarget_m68k) *** 112,117 **** --- 115,125 ---- AM_CONDITIONAL(SIDTARGET_M68K,[test "x$sidtarget_m68k" = x1]) AC_MSG_RESULT($sidtarget_m68k) + AC_MSG_CHECKING(Toshiba MeP family support) + AC_SUBST(sidtarget_mep) + AM_CONDITIONAL(SIDTARGET_MEP,[test "x$sidtarget_mep" = x1]) + AC_MSG_RESULT($sidtarget_mep) + AC_MSG_CHECKING(MT family support) AC_SUBST(sidtarget_mt) AM_CONDITIONAL(SIDTARGET_MT,[test "x$sidtarget_mt" = x1]) Index: sid/main/dynamic/Makefile.am =================================================================== RCS file: /cvs/src/src/sid/main/dynamic/Makefile.am,v retrieving revision 1.15 diff -c -p -r1.15 Makefile.am *** sid/main/dynamic/Makefile.am 30 Nov 2006 18:48:30 -0000 1.15 --- sid/main/dynamic/Makefile.am 11 Jan 2007 19:10:33 -0000 *************** bin_PROGRAMS = sid *** 10,18 **** --- 10,26 ---- TARGETCFGS = shCfg.cxx TARGETDEFINES = + if SIDTARGET_MEP + FAM9LIB = ../../component/families/mep/libmepfamily.la + FAM9LIB2 = -dlpreopen ../../component/families/mep/libmepfamily.la + TARGETCFGS += mepCfg.cxx + TARGETDEFINES += -DSIDTARGET_MEP + endif + if SIDTARGET_SH TARGETDEFINES += -DSIDTARGET_SH endif + if SIDTARGET_SH64 TARGETDEFINES += -DSIDTARGET_SH64 endif Index: sid/main/dynamic/commonCfg.cxx =================================================================== RCS file: /cvs/src/src/sid/main/dynamic/commonCfg.cxx,v retrieving revision 1.20 diff -c -p -r1.20 commonCfg.cxx *** sid/main/dynamic/commonCfg.cxx 23 Oct 2006 21:14:33 -0000 1.20 --- sid/main/dynamic/commonCfg.cxx 11 Jan 2007 19:10:33 -0000 *************** SessionCfg::profile_config (const string *** 831,836 **** --- 831,838 ---- string final_insn_count = "false"; string gprof = ""; string insn_count = "10000"; + // mep-specific options + string model_busses = "false"; // Now examine the spec and reset those which are specified. vectoropts = sidutil::tokenize (parts[1], " "); *************** SessionCfg::profile_config (const string *** 877,882 **** --- 879,887 ---- gprof = profile_opt_gprof_value (opt, opt_parts); else if (match_profile_opt (opt_name, "--insn-count=", 3)) insn_count = profile_opt_int_value (opt, opt_parts); + // mep-specific options + else if (match_profile_opt (opt_name, "--model-busses", 3)) + model_busses = profile_opt_value (opt, opt_parts, 1); } // Now contruct a string representing the complete configuration *************** SessionCfg::profile_config (const string *** 892,898 **** "verbose=" + verbose + ":" + "final-insn-count=" + final_insn_count + ":" + "gprof=" + gprof + ":" + ! "insn-count=" + insn_count); } void SessionCfg::write_config (Writer &w) --- 897,905 ---- "verbose=" + verbose + ":" + "final-insn-count=" + final_insn_count + ":" + "gprof=" + gprof + ":" + ! "insn-count=" + insn_count + ":" + ! // mep-specific options ! "model-busses=" + model_busses); } void SessionCfg::write_config (Writer &w) *************** GprofCfg::GprofCfg (const string name, *** 1016,1022 **** conn_pin (cpu, "cg-callee", this, "cg-callee"); conn_pin (cpu, "gprof-pc-hi", this, "pc-hi"); conn_pin (cpu, "gprof-pc", this, "pc"); ! if (cpu->comp_type().substr(0, 9) == "hw-cpu-sh") set (this, "bucket-size", "2"); // bytes-per-bucket else set (this, "bucket-size", "4"); // bytes-per-bucket --- 1023,1031 ---- conn_pin (cpu, "cg-callee", this, "cg-callee"); conn_pin (cpu, "gprof-pc-hi", this, "pc-hi"); conn_pin (cpu, "gprof-pc", this, "pc"); ! if (cpu->comp_type().substr(0, 10) == "hw-cpu-mep") ! set (this, "bucket-size", "2"); // bytes-per-bucket ! else if (cpu->comp_type().substr(0, 9) == "hw-cpu-sh") set (this, "bucket-size", "2"); // bytes-per-bucket else set (this, "bucket-size", "4"); // bytes-per-bucket *************** GprofCfg::GprofCfg (const string name, *** 1037,1043 **** sess->shutdown_seq->add_output (7, this, "store"); relate (this, "target-component", cpu); ! if (cpu->comp_type().substr(0, 9) == "hw-cpu-sh") set (this, "bucket-size", "2"); // bytes-per-bucket else set (this, "bucket-size", "4"); // bytes-per-bucket --- 1046,1054 ---- sess->shutdown_seq->add_output (7, this, "store"); relate (this, "target-component", cpu); ! if (cpu->comp_type().substr(0, 10) == "hw-cpu-mep") ! set (this, "bucket-size", "2"); // bytes-per-bucket ! else if (cpu->comp_type().substr(0, 9) == "hw-cpu-sh") set (this, "bucket-size", "2"); // bytes-per-bucket else set (this, "bucket-size", "4"); // bytes-per-bucket Index: sid/main/dynamic/commonCfg.h =================================================================== RCS file: /cvs/src/src/sid/main/dynamic/commonCfg.h,v retrieving revision 1.10 diff -c -p -r1.10 commonCfg.h *** sid/main/dynamic/commonCfg.h 11 May 2006 20:27:02 -0000 1.10 --- sid/main/dynamic/commonCfg.h 11 Jan 2007 19:10:33 -0000 *************** public: *** 387,392 **** --- 387,424 ---- virtual void write_load (Writer &w); virtual void write_config (Writer &w); + // Mep-specific options + virtual void set_config_index (unsigned i = 0) {} + virtual void set_warn_write_to_code (bool b = true) {} + virtual void set_warn_write_to_rom (bool b = true) {} + virtual void set_allow_write_to_rom (bool b = true) {} + virtual void set_model_busses (bool b = true) {} + virtual void set_dsp_user_out (bool b = true) {} + virtual void set_corrupt_caches (bool b = true) {} + virtual void set_opt_insn (string s = "") {} + virtual void set_opt_no_insn (string s = "") {} + virtual void set_opt_local_mem (string s = "") {} + virtual void set_opt_global_mem (string s = "") {} + virtual void set_opt_shadow_mem (string s = "") {} + virtual void set_opt_dmac_channel_bitw (string s = "") {} + virtual void set_opt_biu_width (string s = "") {} + virtual void set_opt_dmac_rectangle (bool b = false) {} + virtual void set_opt_imem_size (string s = "") {} + virtual void set_opt_dmem_size (string s = "") {} + virtual void set_opt_dmem_bank_num (string s = "") {} + virtual void set_opt_dmem_fixed_start_address (bool b = false) {} + virtual void set_opt_icache_size (string s = "") {} + virtual void set_opt_icache_line_size (string s = "") {} + virtual void set_opt_icache_way (string s = "") {} + virtual void set_opt_icache_cwf (string s = "") {} + virtual void set_opt_dcache_size (string s = "") {} + virtual void set_opt_dcache_line_size (string s = "") {} + virtual void set_opt_dcache_way (string s = "") {} + virtual void set_opt_dcache_cwf (string s = "") {} + virtual void set_opt_intc_channel_bitw (string s = "") {} + virtual void set_opt_intc_level (string s = "") {} + virtual void set_opt_timer_channel_bitw (string s = "") {} + virtual ~BoardCfg (); GlueSeqCfg *cache_flush_net; Index: sid/main/dynamic/mainDynamic.cxx =================================================================== RCS file: /cvs/src/src/sid/main/dynamic/mainDynamic.cxx,v retrieving revision 1.9 diff -c -p -r1.9 mainDynamic.cxx *** sid/main/dynamic/mainDynamic.cxx 18 Oct 2006 18:46:17 -0000 1.9 --- sid/main/dynamic/mainDynamic.cxx 11 Jan 2007 19:10:36 -0000 *************** *** 13,18 **** --- 13,22 ---- #include #include + #ifdef SIDTARGET_MEP + #include "mepCfg.h" + #endif /* SIDTARGET_MEP */ + #if defined (SIDTARGET_SH) || defined (SIDTARGET_SH64) #include "shCfg.h" #endif /* SIDTARGET_SH */ *************** mk_basic (const string name, SessionCfg *** 41,49 **** --- 45,122 ---- return new BoardCfg (name, "none", sess, false, true, true); } + #ifdef SIDTARGET_MEP + /* begin-mepcfgtool-factories */ + static BoardCfg * + mk_simple (const string name, SessionCfg *sess) + { + MepBoardCfg *b = new MepBoardCfg (name, "simple", sess); + + b->set_core_type (MEP_CORE_C2); + b->set_cpu ("mep-ext1"); + b->add_irq_board (); + b->set_core_id (1); + b->set_intc_channel_bitw (8); + b->set_intc_level (15); + b->set_opt_biu (64); + b->set_endian ("big"); + b->set_opt_abs (false); + b->set_opt_ave (false); + b->set_opt_bit (false); + b->set_opt_clp (false); + b->set_opt_div (false); + b->set_opt_ldz (false); + b->set_opt_min (false); + b->set_opt_mul (false); + b->set_opt_sat (false); + b->set_opt_dsu (false); + b->set_opt_uci (false); + return b; + } + + static BoardCfg * + mk_fmax (const string name, SessionCfg *sess) + { + MepBoardCfg *b = new MepBoardCfg (name, "fmax", sess); + + b->set_core_type (MEP_CORE_C2); + b->set_cpu ("mep-ext2"); + b->add_irq_board (); + b->set_core_id (2); + b->set_intc_channel_bitw (8); + b->set_intc_level (15); + b->add_cop ("fmax_cop", 0); + b->set_cop_data_bus_width (32); + b->set_cop_ccr ( 0, 0x00000101); + b->set_cop_ccr ( 1, 0x00000000); + b->set_cop_ccr (15, 0x00000000); + b->set_opt_biu (64); + b->set_endian ("big"); + b->set_opt_abs (true); + b->set_opt_ave (true); + b->set_opt_bit (true); + b->set_opt_clp (true); + b->set_opt_div (true); + b->set_opt_ldz (true); + b->set_opt_min (true); + b->set_opt_mul (true); + b->set_opt_sat (true); + b->set_opt_dsu (false); + b->set_opt_uci (false); + return b; + } + /* end-mepcfgtool-factories */ + + #endif /* SIDTARGET_MEP */ static boardspec boards [] = { {"basic", "basic cpu + memory board", & mk_basic}, + #ifdef SIDTARGET_MEP + /* begin-mepcfgtool-boards */ + { "simple", "MeP custom board 'simple'", & mk_simple }, + { "fmax", "MeP custom board 'fmax'", & mk_fmax }, + /* end-mepcfgtool-boards */ + #endif /* SIDTARGET_MEP */ #if defined (SIDTARGET_SH) || defined (SIDTARGET_SH64) { "sh", "sh default board", & mk_sh }, { "sh2", "sh2 board", & mk_sh2 }, *************** usage () *** 163,168 **** --- 236,275 ---- cout << "--warmup Start the simulation in 'warm-up' mode" << endl; cout << "--warmup-func=FUNCTIONS" << endl; cout << " Specify functions to be simulated in 'warm-up' mode" << endl; + cout << "--warn-write-to-code Generate a warning when memory containing executable code is written to" << endl; + cout << "--no-warn-write-to-code Do not generate a warning when memory containing executable code is written to" << endl; + cout << "--warn-write-to-rom Generate a warning when read only memory is written to" << endl; + cout << "--allow-write-to-rom Allow read only memory to be written to" << endl; + // MeP-specific options + cout << "--model-busses Turn on bus arbitration modelling" << endl; + cout << "--dsp-user-out Display user written DSP trace output for --trace-disassemble" << endl; + cout << "--no-dsp-user-out Display normal insn disassembly of DSP insns for --trace-disassemble" << endl; + cout << "--local-mem=START,SIZE,NAME[,api]" << endl; + cout << "--global-mem=START,SIZE[,cached][,rom]" << endl; + cout << "--shadow-mem=START,SIZE,BASE[,cached][,MODULE_NAME]" << endl; + cout << "--biu-width=N" << endl; + cout << "--dmac-channel-bitw=N" << endl; + cout << "--dmac-rectangle" << endl; + cout << "--dmac-no-rectangle" << endl; + cout << "--insn=abs|ave|bit|clp|div|ldz|min|mul|sat" << endl; + cout << "--no-insn=abs|ave|bit|clp|div|ldz|min|mul|sat" << endl; + cout << "--imem-size=N" << endl; + cout << "--dmem-size=N" << endl; + cout << "--dmem-bank-num=N" << endl; + cout << "--dmem-fixed-start-address" << endl; + cout << "--dmem-no-fixed-start-address" << endl; + cout << "--icache-size=N" << endl; + cout << "--icache-line-size=N" << endl; + cout << "--icache-way=N" << endl; + cout << "--icache-cwf=on|off" << endl; + cout << "--dcache-size=N" << endl; + cout << "--dcache-line-size=N" << endl; + cout << "--dcache-way=N" << endl; + cout << "--dcache-cwf=on|off" << endl; + cout << "--corrupt-caches" << endl; + cout << "--intc-channel-bitw=N" << endl; + cout << "--intc-level=N" << endl; + cout << "--timer-channel-bitw=N" << endl; cout << endl << " note: most board-specific options can be used in board-neutral position " << endl << " where they are interpreted as session-specific or default settings. " << endl; *************** struct Defs { *** 515,520 **** --- 622,635 ---- profile_func (""), warmup_func (""), start_config (""), + warn_write_to_code (true), + warn_write_to_rom (false), + allow_write_to_rom (false), + // MeP-specific + model_busses (false), + dsp_user_out (false), + corrupt_caches (false), + // End MeP-specific step_insn_count ("10000") {} string cpu; *************** struct Defs { *** 533,538 **** --- 648,660 ---- string warmup_func; string start_config; string step_insn_count; + bool warn_write_to_code; + bool warn_write_to_rom; + bool allow_write_to_rom; + // MeP-specific + bool model_busses; + bool dsp_user_out; + bool corrupt_caches; }; struct BoardConfig *************** main(int argc, char* argv[]) *** 587,593 **** opt_trace_disassemble, opt_trace_counter, opt_trace_core, opt_final_insn_count, opt_eb, opt_el, opt_gprof, opt_ulog_level, opt_ulog_mode, opt_ulog_file, ! opt_warmup, opt_warmup_func }; int curr_opt; --- 709,730 ---- opt_trace_disassemble, opt_trace_counter, opt_trace_core, opt_final_insn_count, opt_eb, opt_el, opt_gprof, opt_ulog_level, opt_ulog_mode, opt_ulog_file, ! opt_warmup, opt_warmup_func, ! opt_warn_write_to_code, no_opt_warn_write_to_code, ! opt_warn_write_to_rom, opt_allow_write_to_rom, ! // Mep-specific options ! opt_model_busses, ! opt_dsp_user_out, opt_no_dsp_user_out, ! opt_local_mem, opt_global_mem, opt_shadow_mem, ! opt_biu_width, opt_insn, opt_no_insn, ! opt_imem_size, opt_dmem_size, opt_dmem_bank_num, ! opt_dmem_fixed_start_address, opt_dmem_no_fixed_start_address, ! opt_icache_size, opt_icache_line_size, opt_icache_way, opt_icache_cwf, ! opt_dcache_size, opt_dcache_line_size, opt_dcache_way, opt_dcache_cwf, ! opt_dmac_channel_bitw, opt_dmac_rectangle, opt_dmac_no_rectangle, ! opt_corrupt_caches, ! opt_intc_channel_bitw, opt_intc_level, ! opt_timer_channel_bitw }; int curr_opt; *************** main(int argc, char* argv[]) *** 639,644 **** --- 776,815 ---- {"ulog-file", required_argument, &curr_opt, opt_ulog_file }, {"warmup", no_argument, &curr_opt, opt_warmup }, {"warmup-func", required_argument, &curr_opt, opt_warmup_func }, + {"warn-write-to-code",no_argument, & curr_opt, opt_warn_write_to_code }, + {"no-warn-write-to-code",no_argument, & curr_opt, no_opt_warn_write_to_code }, + {"warn-write-to-rom",no_argument, & curr_opt, opt_warn_write_to_rom }, + {"allow-write-to-rom",no_argument, & curr_opt, opt_allow_write_to_rom }, + // Mep-specific options + {"model-busses",no_argument, & curr_opt, opt_model_busses }, + {"dsp-user-out",no_argument, & curr_opt, opt_dsp_user_out }, + {"no-dsp-user-out",no_argument, & curr_opt, opt_no_dsp_user_out }, + {"local-mem",required_argument, & curr_opt, opt_local_mem }, + {"global-mem",required_argument, & curr_opt, opt_global_mem }, + {"shadow-mem",required_argument, & curr_opt, opt_shadow_mem }, + {"dmac-channel-bitw",required_argument, & curr_opt, opt_dmac_channel_bitw }, + {"biu-width",required_argument, & curr_opt, opt_biu_width }, + {"dmac-rectangle",no_argument, & curr_opt, opt_dmac_rectangle }, + {"dmac-no-rectangle",no_argument, & curr_opt, opt_dmac_no_rectangle }, + {"insn",required_argument, & curr_opt, opt_insn }, + {"no-insn",required_argument, & curr_opt, opt_no_insn }, + {"imem-size",required_argument, & curr_opt, opt_imem_size }, + {"dmem-size",required_argument, & curr_opt, opt_dmem_size }, + {"dmem-bank-num",required_argument, & curr_opt, opt_dmem_bank_num }, + {"dmem-fixed-start-address",no_argument, & curr_opt, opt_dmem_fixed_start_address }, + {"dmem-no-fixed-start-address",no_argument, & curr_opt, opt_dmem_no_fixed_start_address }, + {"icache-size",required_argument, & curr_opt, opt_icache_size }, + {"icache-line-size",required_argument, & curr_opt, opt_icache_line_size }, + {"icache-way",required_argument, & curr_opt, opt_icache_way }, + {"icache-cwf",required_argument, & curr_opt, opt_icache_cwf }, + {"dcache-size",required_argument, & curr_opt, opt_dcache_size }, + {"dcache-line-size",required_argument, & curr_opt, opt_dcache_line_size }, + {"dcache-way",required_argument, & curr_opt, opt_dcache_way }, + {"dcache-cwf",required_argument, & curr_opt, opt_dcache_cwf }, + {"corrupt-caches",no_argument, & curr_opt, opt_corrupt_caches }, + {"intc-channel-bitw",required_argument, & curr_opt, opt_intc_channel_bitw }, + {"intc-level",required_argument, & curr_opt, opt_intc_level }, + {"timer-channel-bitw",required_argument, & curr_opt, opt_timer_channel_bitw }, { 0, 0, NULL, 0 } }; *************** main(int argc, char* argv[]) *** 730,735 **** --- 901,922 ---- curr_board->add_profile_func (defaults.profile_func); if (defaults.step_insn_count != "10000") curr_board->set_step_insn_count(defaults.step_insn_count); + if (defaults.warn_write_to_code) + curr_board->set_warn_write_to_code(true); + else + curr_board->set_warn_write_to_code(false); + if (defaults.warn_write_to_rom) + curr_board->set_warn_write_to_rom(true); + if (defaults.allow_write_to_rom) + curr_board->set_allow_write_to_rom(true); + // Mep-specific options + curr_board->set_config_index (i - boards); + if (defaults.model_busses) + curr_board->set_model_busses(true); + if (defaults.dsp_user_out) + curr_board->set_dsp_user_out(true); + if (defaults.corrupt_caches) + curr_board->set_corrupt_caches(true); break; } } *************** main(int argc, char* argv[]) *** 1034,1039 **** --- 1221,1437 ---- need_sess (sess, verbose_p); sess->profile_config (optstring ()); break; + + case opt_warn_write_to_code: + if (curr_board) + curr_board->set_warn_write_to_code (true); + else + defaults.warn_write_to_code = true; + break; + + case no_opt_warn_write_to_code: + if (curr_board) + curr_board->set_warn_write_to_code (false); + else + defaults.warn_write_to_code = false; + break; + + case opt_warn_write_to_rom: + if (curr_board) + curr_board->set_warn_write_to_rom (true); + else + defaults.warn_write_to_rom = true; + break; + + case opt_allow_write_to_rom: + if (curr_board) + curr_board->set_allow_write_to_rom (true); + else + defaults.allow_write_to_rom = true; + break; + + // Mep-specific options. + case opt_model_busses: + if (curr_board) + { + curr_board->set_model_busses (true); + board_start_config += " --model-busses"; + } + else + { + defaults.model_busses = true; + defaults.start_config += " --model-busses"; + } + break; + + case opt_dsp_user_out: + if (curr_board) + curr_board->set_dsp_user_out (true); + else + defaults.dsp_user_out = true; + break; + + case opt_no_dsp_user_out: + if (curr_board) + curr_board->set_dsp_user_out (false); + else + defaults.dsp_user_out = false; + break; + + case opt_local_mem: + if (curr_board) + curr_board->set_opt_local_mem (optstring ()); + break; + + case opt_global_mem: + if (curr_board) + curr_board->set_opt_global_mem (optstring ()); + break; + + case opt_shadow_mem: + if (curr_board) + curr_board->set_opt_shadow_mem (optstring ()); + break; + + case opt_dmac_channel_bitw: + if (curr_board) + curr_board->set_opt_dmac_channel_bitw (optstring ()); + break; + + case opt_biu_width: + if (curr_board) + curr_board->set_opt_biu_width (optstring ()); + break; + + case opt_dmac_rectangle: + if (curr_board) + curr_board->set_opt_dmac_rectangle (true); + break; + + case opt_dmac_no_rectangle: + if (curr_board) + curr_board->set_opt_dmac_rectangle (false); + break; + + case opt_insn: + if (curr_board) + curr_board->set_opt_insn (optstring ()); + break; + + case opt_no_insn: + if (curr_board) + curr_board->set_opt_no_insn (optstring ()); + break; + + case opt_imem_size: + if (curr_board) + curr_board->set_opt_imem_size (optstring ()); + break; + + case opt_dmem_size: + if (curr_board) + curr_board->set_opt_dmem_size (optstring ()); + break; + + case opt_dmem_bank_num: + if (curr_board) + curr_board->set_opt_dmem_bank_num (optstring ()); + break; + + case opt_dmem_fixed_start_address: + if (curr_board) + curr_board->set_opt_dmem_fixed_start_address (true); + break; + + case opt_dmem_no_fixed_start_address: + if (curr_board) + curr_board->set_opt_dmem_fixed_start_address (false); + break; + + case opt_icache_size: + if (curr_board) + curr_board->set_opt_icache_size (optstring ()); + break; + + case opt_icache_line_size: + if (curr_board) + curr_board->set_opt_icache_line_size (optstring ()); + break; + + case opt_icache_way: + if (curr_board) + curr_board->set_opt_icache_way (optstring ()); + break; + + case opt_icache_cwf: + { + string cwf = optstring(); + if (cwf == "on" || cwf == "off") + { + if (curr_board) + curr_board->set_opt_icache_cwf (cwf); + } + else + { + cerr << "error: --icache-cwf must be either on or off" << endl; + exit (8); + } + } + break; + + case opt_dcache_size: + if (curr_board) + curr_board->set_opt_dcache_size (optstring ()); + break; + + case opt_dcache_line_size: + if (curr_board) + curr_board->set_opt_dcache_line_size (optstring ()); + break; + + case opt_dcache_way: + if (curr_board) + curr_board->set_opt_dcache_way (optstring ()); + break; + + case opt_dcache_cwf: + { + string cwf = optstring(); + if (cwf == "on" || cwf == "off") + { + if (curr_board) + curr_board->set_opt_dcache_cwf (cwf); + } + else + { + cerr << "error: --dcache-cwf must be either on or off" << endl; + exit (8); + } + } + break; + + case opt_corrupt_caches: + if (curr_board) + curr_board->set_corrupt_caches (true); + else + defaults.corrupt_caches = true; + break; + + case opt_intc_channel_bitw: + if (curr_board) + curr_board->set_opt_intc_channel_bitw (optstring ()); + break; + + case opt_intc_level: + if (curr_board) + curr_board->set_opt_intc_level (optstring ()); + break; + + case opt_timer_channel_bitw: + if (curr_board) + curr_board->set_opt_timer_channel_bitw (optstring ()); + break; + // End Mep-specific options. } break;