From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26744 invoked by alias); 17 Jun 2005 11:03:24 -0000 Mailing-List: contact sid-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sources.redhat.com Received: (qmail 26711 invoked by uid 22791); 17 Jun 2005 11:03:17 -0000 Received: from mail.it.axis.com (HELO bart.se.axis.com) (193.13.178.9) by sourceware.org (qpsmtpd/0.30-dev) with ESMTP; Fri, 17 Jun 2005 11:03:16 +0000 Received: from bart.se.axis.com (bart.se.axis.com [127.0.0.1]) by bart.se.axis.com (Postfix) with ESMTP id 82B0863AC7; Fri, 17 Jun 2005 13:03:01 +0200 (CEST) Received: from PCSTARVIK (dh10-84-127-78.se.axis.com [10.84.127.78]) by bart.se.axis.com (Postfix) with ESMTP id 5909263A88; Fri, 17 Jun 2005 13:03:01 +0200 (CEST) From: "Mikael Starvik" To: "'Frank Ch. Eigler'" Cc: Subject: RE: Future of SID Date: Fri, 17 Jun 2005 11:03:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_000F_01C5733C.EBB66B80" In-Reply-To: X-Virus-Checked: Checked by ClamAV on sourceware.org X-SW-Source: 2005-q2/txt/msg00043.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_000F_01C5733C.EBB66B80 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-length: 1028 Long time since this email conversation took place but anyway. I have attached the SID configuration files that we use to set up an entire system with CPU, MMU, Ethernet etc that runs Linux 2.6. I have also attached the small file we use to add a second CPU and run SMP. Works like a charm :-) The components are not quite ready for submission yet. /Mikael -----Original Message----- From: Frank Ch. Eigler [mailto:fche@redhat.com] Sent: Wednesday, March 30, 2005 12:16 AM To: Mikael Starvik Cc: sid@sources.redhat.com Subject: Re: Future of SID Hi - On Tue, Mar 29, 2005 at 09:33:21AM +0200, Mikael Starvik wrote: > [...] > During the development of a new System-On-Chip ASIC we have developed SID > components of most parts of the system including CPU, MMU, DMA, Ethernet, > UART etc. We have used this to develop a working Linux port [...] Wonderful! Do you expect to be able to eventually share any of this modelling effort outside Axis? Even just the sid configuration files you use would be informative. - FChE ------=_NextPart_000_000F_01C5733C.EBB66B80 Content-Type: application/octet-stream; name="linux.conf" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="linux.conf" Content-length: 22101 # Load libraries=0A= load libcache.la cache_component_library=0A= load libcgencpu.la cgen_component_library=0A= load libconsoles.la console_component_library=0A= load libdma.la dma_component_library=0A= load libethernet.la ethernet_component_library=0A= load libgdb.la gdb_component_library=0A= load libgloss.la gloss_component_library=0A= load libglue.la glue_component_library=0A= load libgpio.la gpio_component_library=0A= load libinterrupt.la interrupt_component_library=0A= load libloader.la loader_component_library=0A= load libmapper.la mapper_component_library=0A= load libmemory.la mem_component_library=0A= load libmmu.la mmu_component_library=0A= load libprof.la prof_component_library=0A= load libsched.la sched_component_library=0A= load libtimers.la timer_component_library=0A= load libuart.la uart_component_library=0A= load libcrypto_accel.la crypto_component_library=0A= load libfamilies.la families_component_library=0A= =0A= set main persistent? false=0A= =0A= # Allocate components=0A= new hw-cpu-crisv32 cpu=0A= new hw-mmu-crisv32 insn-mmu=0A= new hw-mmu-crisv32 data-mmu=0A= new hw-mapper-basic cpu-mapper=0A= new hw-glue-sequence-8 init-sequence=0A= new hw-glue-sequence-8 hw-reset-net=0A= new hw-glue-sequence-8 deinit-sequence=0A= new hw-glue-sequence-1 yield-net=0A= new hw-glue-sequence-2 cache-flush-net=0A= new sid-sched-host-accurate host-sched=0A= new sid-sched-sim target-sched=0A= new hw-dma-crisv32 dma0=0A= new hw-dma-crisv32 dma1=0A= new hw-dma-crisv32 dma2=0A= new hw-dma-crisv32 dma3=0A= new hw-dma-crisv32 dma4=0A= new hw-dma-crisv32 dma5=0A= new hw-dma-crisv32 dma6=0A= new hw-dma-crisv32 dma7=0A= new hw-dma-crisv32 dma8=0A= new hw-dma-crisv32 dma9=0A= new hw-dmafifo-crisv32 fifo0=0A= new hw-dmafifo-crisv32 fifo1=0A= new hw-dmafifo-crisv32 fifo2=0A= new hw-dmafifo-crisv32 fifo3=0A= new hw-dmafifo-crisv32 fifo4=0A= new hw-dmafifo-crisv32 fifo5=0A= new hw-dmafifo-crisv32 fifo6=0A= new hw-dmafifo-crisv32 fifo7=0A= new hw-dmafifo-crisv32 fifo8=0A= new hw-dmafifo-crisv32 fifo9=0A= new hw-ethernet-crisv32 eth0=0A= new hw-ethernet-crisv32 eth1=0A= new hw-uart-crisv32 ser0=0A= new hw-uart-crisv32 ser1=0A= new hw-uart-crisv32 ser2=0A= new hw-uart-crisv32 ser3=0A= new hw-crypto-crisv32 strcop=0A= new hw-timer-crisv32 timer=0A= new hw-interrupt-crisv32 irq=0A= new hw-gpio-crisv32 gpio=0A= new hw-memory-flash-am29bds323d cse0=0A= new hw-memory-flash-am29bds323d cse1=0A= new hw-memory-nandflash-samsung_2816 nand_flash=0A= new hw-memory-ram/rom-basic sdram=0A= new hw-memory-ram/rom-basic intram=0A= new hw-memory-ram/rom-basic bootrom=0A= new hw-memory-ram/rom-basic dummy=0A= new hw-config_regs-crisv32 config_regs=0A= =0A= # Global connections=0A= set host-sched num-clients 10 # large enough?=0A= set target-sched num-clients 10 # large enough?=0A= connect-pin main perform-activity -> host-sched advance=0A= connect-pin main perform-activity -> target-sched advance=0A= connect-pin main starting -> init-sequence input=0A= connect-pin main stopping -> deinit-sequence input=0A= connect-pin init-sequence output-0 -> hw-reset-net input=0A= connect-pin hw-reset-net output-0 -> cpu reset!=0A= connect-pin hw-reset-net output-1 -> insn-mmu reset=20=0A= connect-pin hw-reset-net output-2 -> data-mmu reset=0A= connect-pin yield-net output-0 -> cpu yield=0A= connect-pin yield-net output-0 -> host-sched yield=0A= =0A= # Scheduler=0A= connect-pin target-sched 0-event -> cpu step!=0A= connect-pin target-sched 0-control <- cpu step-cycles=0A= connect-pin target-sched time-query <- cpu time-query=0A= connect-pin target-sched time-high -> cpu time-high=0A= connect-pin target-sched time-low -> cpu time-low=0A= set host-sched 0-regular? 1=0A= set host-sched 0-time 150 # apprx. human perception limit=0A= =0A= # CPU=0A= set cpu step-insn-count 10000=0A= set cpu engine-type pbb=0A= set cpu endian little=0A= =0A= # MMUs=0A= connect-bus insn-mmu all cpu-mapper access-port=0A= connect-bus data-mmu all cpu-mapper access-port=0A= connect-bus cpu insn-memory insn-mmu access-port=0A= connect-pin cpu user -> insn-mmu user=0A= connect-pin cpu pid -> insn-mmu pid=0A= connect-pin cpu enable-insn-mmu -> insn-mmu enable=0A= connect-bus cpu support-function-register-bank-1 insn-mmu registers=0A= connect-pin insn-mmu refill_fault -> cpu insn-refill-fault=0A= connect-pin insn-mmu invalid_fault -> cpu insn-invalidaddr-fault=0A= connect-pin insn-mmu access_fault -> cpu insn-access-fault=0A= connect-pin insn-mmu ex_fault -> cpu insn-ex-fault=0A= connect-pin insn-mmu fault_address -> cpu insn-fault-address=0A= set insn-mmu accesses-are-fetches true=0A= connect-bus cpu data-memory data-mmu access-port=0A= connect-pin cpu user -> data-mmu user=0A= connect-pin cpu pid -> data-mmu pid=0A= connect-pin cpu enable-data-mmu -> data-mmu enable=0A= connect-bus cpu support-function-register-bank-2 data-mmu registers=0A= connect-pin data-mmu refill_fault -> cpu data-refill-fault=0A= connect-pin data-mmu invalid_fault -> cpu data-invalidaddr-fault=0A= connect-pin data-mmu access_fault -> cpu data-access-fault=0A= connect-pin data-mmu we_fault -> cpu data-we-fault=0A= connect-pin data-mmu fault_address -> cpu data-fault-address=0A= =0A= # Ethernet interface 0=0A= connect-pin hw-reset-net output-0 -> eth0 reset=0A= connect-pin hw-reset-net output-0 -> fifo0 reset=0A= connect-pin hw-reset-net output-0 -> fifo1 reset=0A= connect-pin hw-reset-net output-0 -> dma0 reset=0A= connect-pin hw-reset-net output-0 -> dma1 reset=0A= connect-pin dma0 data_out -> fifo0 data_in=0A= connect-pin dma0 eop_out -> fifo0 write_eop=0A= connect-pin dma0 wait_out -> fifo0 write_wait=0A= connect-bus dma0 memif cpu-mapper access-port=0A= connect-bus dma1 memif cpu-mapper access-port=0A= connect-pin fifo0 data_out -> eth0 data_out=0A= connect-pin fifo0 read_eop -> eth0 eop_out=0A= connect-pin fifo0 read_wait -> eth0 wait=0A= connect-pin fifo1 read_eop -> dma1 eop_in=0A= connect-pin fifo1 read_wait -> dma0 wait_ack=0A= connect-pin fifo1 data_out -> dma1 data_in=0A= connect-pin eth0 data_in -> fifo1 data_in=0A= connect-pin eth0 eop_in -> fifo1 write_eop=0A= connect-pin eth0 wait_ack -> fifo1 write_wait=0A= connect-pin main perform-activity -> eth0 check=0A= set dma0 direction? 0=0A= set dma1 direction? 1=0A= set eth0 device eth0=0A= =0A= # Ethernet interface 1=0A= connect-pin hw-reset-net output-0 -> eth1 reset=0A= connect-pin hw-reset-net output-0 -> fifo6 reset=0A= connect-pin hw-reset-net output-0 -> fifo7 reset=0A= connect-pin hw-reset-net output-0 -> dma6 reset=0A= connect-pin hw-reset-net output-0 -> dma7 reset=0A= connect-pin dma6 data_out -> fifo6 data_in=0A= connect-pin dma6 eop_out -> fifo6 write_eop=0A= connect-pin dma6 wait_out -> fifo6 write_wait=0A= connect-bus dma6 memif cpu-mapper access-port=0A= connect-bus dma7 memif cpu-mapper access-port=0A= connect-pin fifo6 data_out -> eth1 data_out=0A= connect-pin fifo6 read_eop -> eth1 eop_out=0A= connect-pin fifo6 read_wait -> eth1 wait=0A= connect-pin fifo7 read_eop -> dma7 eop_in=0A= connect-pin fifo7 read_wait -> dma6 wait_ack=0A= connect-pin fifo7 data_out -> dma7 data_in=0A= connect-pin eth1 data_in -> fifo7 data_in=0A= connect-pin eth1 eop_in -> fifo7 write_eop=0A= connect-pin eth1 wait_ack -> fifo7 write_wait=0A= connect-pin main perform-activity -> eth1 check=0A= set dma6 direction? 0=0A= set dma7 direction? 1=0A= set eth1 device eth1=0A= =0A= # Serial port 0 (manual mode)=0A= connect-pin hw-reset-net output-0 -> ser0 reset=0A= connect-pin main perform-activity -> ser0 check=0A= set ser0 device /dev/ttyS0=0A= set ser0 slowdown 2=0A= set ser0 speedup 1=0A= =0A= # Serial port 1 (DMA)=0A= connect-pin hw-reset-net output-0 -> ser1 reset=0A= connect-pin hw-reset-net output-0 -> fifo4 reset=0A= connect-pin hw-reset-net output-0 -> fifo5 reset=0A= connect-pin hw-reset-net output-0 -> dma4 reset=0A= connect-pin hw-reset-net output-0 -> dma5 reset=0A= connect-pin dma4 data_out -> fifo4 data_in=0A= connect-pin dma4 eop_out -> fifo4 write_eop=0A= connect-pin dma4 wait_out -> fifo4 write_wait=0A= connect-bus dma4 memif cpu-mapper access-port=0A= connect-bus dma5 memif cpu-mapper access-port=0A= connect-pin dma5 stop_input -> fifo5 stop_output=0A= connect-pin fifo4 stop_input -> dma4 stop_output=0A= connect-pin fifo4 data_out -> ser1 data_out=0A= connect-pin fifo4 read_wait -> ser1 wait=0A= connect-pin fifo5 data_out -> dma5 data_in=0A= connect-pin fifo5 read_eop -> dma5 eop_in=0A= connect-pin fifo5 read_wait -> dma4 wait_ack=0A= connect-pin ser1 data_in -> fifo5 data_in=0A= connect-pin ser1 wait_ack -> fifo5 write_wait=0A= connect-pin ser1 stop_output -> fifo4 stop_output=0A= connect-pin ser1 receive_timeout -> fifo5 flush_eop=0A= connect-pin main perform-activity -> ser1 check=0A= connect-pin ser1 receive_timer-control -> target-sched 1-control=0A= connect-pin target-sched 1-event -> ser1 receive_timer-event=0A= set dma4 direction? 0=0A= set dma5 direction? 1=0A= set ser1 device /dev/ttyS1=0A= set ser1 slowdown 2=0A= set ser1 speedup 1=0A= =0A= # Serial port 2 (DMA)=0A= connect-pin hw-reset-net output-0 -> ser2 reset=0A= connect-pin hw-reset-net output-0 -> fifo2 reset=0A= connect-pin hw-reset-net output-0 -> fifo3 reset=0A= connect-pin hw-reset-net output-0 -> dma2 reset=0A= connect-pin hw-reset-net output-0 -> dma3 reset=0A= connect-pin dma2 data_out -> fifo2 data_in=0A= connect-pin dma2 eop_out -> fifo2 write_eop=0A= connect-pin dma2 wait_out -> fifo2 write_wait=0A= connect-bus dma2 memif cpu-mapper access-port=0A= connect-bus dma3 memif cpu-mapper access-port=0A= connect-pin dma3 stop_input -> fifo3 stop_output=0A= connect-pin fifo2 stop_input -> dma2 stop_output=0A= connect-pin fifo2 data_out -> ser2 data_out=0A= connect-pin fifo2 read_wait -> ser2 wait=0A= connect-pin fifo3 data_out -> dma3 data_in=0A= connect-pin fifo3 read_eop -> dma3 eop_in=0A= connect-pin fifo3 read_wait -> dma2 wait_ack=0A= connect-pin ser2 data_in -> fifo3 data_in=0A= connect-pin ser2 wait_ack -> fifo3 write_wait=0A= connect-pin ser2 stop_output -> fifo2 stop_output=0A= connect-pin ser2 receive_timeout -> fifo3 flush_eop=0A= connect-pin main perform-activity -> ser2 check=0A= connect-pin ser2 receive_timer-control -> target-sched 2-control=0A= connect-pin target-sched 2-event -> ser2 receive_timer-event=0A= set dma2 direction? 0=0A= set dma3 direction? 1=0A= set ser2 device /dev/ttyS2=0A= set ser2 slowdown 2=0A= set ser2 speedup 1=0A= =0A= # Serial port 3 (manual mode)=0A= connect-pin hw-reset-net output-0 -> ser3 reset=0A= connect-pin main perform-activity -> ser3 check=0A= set ser3 device /dev/ttyS3=0A= set ser3 slowdown 2=0A= set ser3 speedup 1=0A= =0A= # Strcop=0A= connect-pin hw-reset-net output-0 -> strcop reset=0A= connect-pin hw-reset-net output-0 -> fifo8 reset=0A= connect-pin hw-reset-net output-0 -> fifo9 reset=0A= connect-pin hw-reset-net output-0 -> dma8 reset=0A= connect-pin hw-reset-net output-0 -> dma9 reset=0A= connect-pin dma8 data_out -> fifo8 data_in=0A= connect-pin dma8 eop_out -> fifo8 write_eop=0A= connect-pin dma8 wait_out -> fifo8 write_wait=0A= connect-bus dma8 memif cpu-mapper access-port=0A= connect-bus dma8 metadata strcop metadata_out=0A= connect-bus dma9 memif cpu-mapper access-port=0A= connect-bus dma9 metadata strcop metadata_in=0A= connect-pin dma9 stop_input -> fifo9 stop_output=0A= connect-pin fifo8 stop_input -> dma8 stop_output=0A= connect-pin fifo8 data_out -> strcop data_out=0A= connect-pin fifo8 read_eop -> strcop eop_out=0A= connect-pin fifo8 read_wait -> strcop wait=0A= connect-pin fifo9 read_eop -> dma9 eop_in=0A= connect-pin fifo9 read_wait -> dma8 wait_ack=0A= connect-pin fifo9 data_out -> dma9 data_in=0A= connect-pin strcop data_in -> fifo9 data_in=0A= connect-pin strcop eop_in -> fifo9 write_eop=0A= connect-pin strcop wait_ack -> fifo9 write_wait=0A= connect-pin strcop force_flush -> fifo9 flush=0A= connect-pin strcop force_flush_eop -> fifo9 flush_eop=0A= set dma8 direction? 0=0A= set dma9 direction? 1=0A= =0A= # Timer=0A= connect-pin hw-reset-net output-0 -> timer reset=0A= connect-pin timer timer0-control -> target-sched 3-control=0A= connect-pin target-sched 3-event -> timer timer0-event=0A= connect-pin timer timer1-control -> target-sched 4-control=0A= connect-pin target-sched 4-event -> timer timer1-event=0A= connect-pin timer trig-control -> target-sched 5-control=0A= connect-pin target-sched 5-event -> timer trig-event=0A= connect-pin timer watchdog-control -> target-sched 6-control=0A= connect-pin target-sched 6-event -> timer watchdog-event=0A= connect-pin timer nmi -> cpu nmi=0A= connect-pin timer reset_out -> init-sequence input=0A= set timer slowdown 2=0A= set timer speedup 1=0A= set timer nmi_polarity 1=0A= =0A= # Interrupt=0A= connect-pin hw-reset-net output-0 -> irq reset=0A= connect-pin dma0 irq_out -> irq irq6=0A= connect-pin dma1 irq_out -> irq irq7=0A= connect-pin dma2 irq_out -> irq irq8=0A= connect-pin dma3 irq_out -> irq irq9=0A= connect-pin dma4 irq_out -> irq irq10=0A= connect-pin dma5 irq_out -> irq irq11=0A= connect-pin dma6 irq_out -> irq irq12=0A= connect-pin dma7 irq_out -> irq irq13=0A= connect-pin dma8 irq_out -> irq irq14=0A= connect-pin dma9 irq_out -> irq irq15=0A= connect-pin ser0 irq_out -> irq irq19=0A= connect-pin ser1 irq_out -> irq irq20=0A= connect-pin ser2 irq_out -> irq irq21=0A= connect-pin ser3 irq_out -> irq irq22=0A= connect-pin timer irq -> irq irq26=0A= connect-pin irq irq_out -> cpu irq=0A= connect-bus cpu irq_vector irq irq_vector=0A= set irq polarity 1=0A= =0A= # NAND flash=0A= connect-pin gpio pa5 -> nand_flash cle=0A= connect-pin gpio pa6 -> nand_flash ale=0A= connect-pin nand_flash busy -> gpio pa7=20=0A= connect-pin hw-reset-net output-0 -> nand_flash reset=0A= =0A= # Config registers=0A= connect-pin hw-reset-net output-0 -> config_regs reset=0A= =0A= # Memory map=0A= set cse0 image-file flash1=0A= set cse1 image-file flash2=0A= connect-pin init-sequence output-1 -> cse1 image-load=0A= connect-bus cpu-mapper cse0:[0x00000000,0x003fffff] cse0 read-write-port=0A= connect-bus cpu-mapper cse0:[0x80000000,0x803fffff] cse0 read-write-port=0A= connect-bus cpu-mapper cse1:[0x04000000,0x043fffff] cse1 read-write-port=0A= connect-bus cpu-mapper cse1:[0x84000000,0x843fffff] cse1 read-write-port=0A= connect-bus cpu-mapper csp0:[0x90000000,0x90ffffff] nand_flash read-write-p= ort=0A= connect-bus cpu-mapper csp1:[0x94000000,0x94ffffff] nand_flash read-write-p= ort=0A= set sdram size 33554432=0A= set sdram image-file kimage=0A= connect-bus cpu-mapper sdram:[0x40000000,0x42000000] sdram read-write-port= =0A= connect-bus cpu-mapper sdram:[0xc0000000,0xc2000000] sdram read-write-port= =0A= set intram size 131072=0A= connect-bus cpu-mapper intram:[0x38000000,0x38020000] intram read-write-por= t=0A= set bootrom size 16384=0A= set bootrom image-file bootrom.ima=0A= connect-bus cpu-mapper intram:[0x3c000000,0x3c004000] bootrom read-write-po= rt=0A= =0A= connect-pin init-sequence output-1 -> cse0 image-load=0A= connect-pin init-sequence output-1 -> sdram image-load=0A= connect-pin init-sequence output-1 -> bootrom image-load=0A= =0A= # The Linux kernel tries to probe flashes at addresses that are not=0A= # mapped. The dummy devices below prevents SID from exiting due to=0A= # unmapped address access.=0A= set dummy size 8192=0A= connect-bus cpu-mapper dummy:[0x80400000,0x80400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x80600000,0x80600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x80800000,0x80800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x80a00000,0x80a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x80c00000,0x80c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x80e00000,0x80e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81000000,0x81000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81200000,0x81200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81400000,0x81400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81600000,0x81600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81800000,0x81800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81a00000,0x81a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81c00000,0x81c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x81e00000,0x81e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82000000,0x82000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82200000,0x82200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82400000,0x82400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82600000,0x82600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82800000,0x82800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82a00000,0x82a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82c00000,0x82c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x82e00000,0x82e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83000000,0x83000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83200000,0x83200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83400000,0x83400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83600000,0x83600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83800000,0x83800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83a00000,0x83a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83c00000,0x83c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x83e00000,0x83e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84400000,0x84400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84600000,0x84600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84800000,0x84800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84a00000,0x84a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84c00000,0x84c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x84e00000,0x84e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85000000,0x85000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85200000,0x85200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85400000,0x85400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85600000,0x85600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85800000,0x85800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85a00000,0x85a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85c00000,0x85c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x85e00000,0x85e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86000000,0x86000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86200000,0x86200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86400000,0x86400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86600000,0x86600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86800000,0x86800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86a00000,0x86a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86c00000,0x86c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x86e00000,0x86e00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87000000,0x87000fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87200000,0x87200fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87400000,0x87400fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87600000,0x87600fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87800000,0x87800fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87a00000,0x87a00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87c00000,0x87c00fff] dummy read-write-port= =0A= connect-bus cpu-mapper dummy:[0x87e00000,0x87e00fff] dummy read-write-port= =0A= =0A= # Mode registers=0A= connect-bus cpu-mapper dma0:[0xb0000000,0xb0001fff] dma0 registers=0A= connect-bus cpu-mapper dma1:[0xb0002000,0xb0003fff] dma1 registers=0A= connect-bus cpu-mapper dma2:[0xb0004000,0xb0005fff] dma2 registers=0A= connect-bus cpu-mapper dma3:[0xb0006000,0xb0007fff] dma3 registers=0A= connect-bus cpu-mapper dma4:[0xb0008000,0xb0009fff] dma4 registers=0A= connect-bus cpu-mapper dma5:[0xb000a000,0xb000bfff] dma5 registers=0A= connect-bus cpu-mapper dma6:[0xb000c000,0xb000dfff] dma6 registers=0A= connect-bus cpu-mapper dma7:[0xb000e000,0xb000ffff] dma7 registers=0A= connect-bus cpu-mapper dma8:[0xb0010000,0xb0011fff] dma8 registers=0A= connect-bus cpu-mapper dma9:[0xb0012000,0xb0013fff] dma9 registers=0A= connect-bus cpu-mapper gpio:[0xb001a000,0xb001bfff] gpio registers=0A= connect-bus cpu-mapper timer:[0xb001e000,0xb001ffff] timer registers=0A= connect-bus cpu-mapper irq:[0xb001c000,0xb001dfff] irq registers=0A= connect-bus cpu-mapper ser0:[0xb0026000,0xb0027fff] ser0 registers=0A= connect-bus cpu-mapper ser1:[0xb0028000,0xb0029fff] ser1 registers=0A= connect-bus cpu-mapper ser2:[0xb002a000,0xb002bfff] ser2 registers=0A= connect-bus cpu-mapper ser3:[0xb002c000,0xb002dfff] ser3 registers=0A= connect-bus cpu-mapper strcop:[0xb0030000,0xb0031fff] strcop registers=0A= connect-bus cpu-mapper eth0:[0xb0034000,0xb0035fff] eth0 registers=0A= connect-bus cpu-mapper eth1:[0xb0036000,0xb0037fff] eth1 registers=0A= # Set up dummy memory for mode registers not modelled=0A= connect-bus cpu-mapper bif_core:[0xb0014000,0xb0015fff] dummy read-write-po= rt=0A= connect-bus cpu-mapper strmux:[0xb003a000,0xb003bfff] dummy read-write-port= =0A= connect-bus cpu-mapper config:[0xb003c000,0xb003dfff] config_regs registers= =0A= connect-bus cpu-mapper marb:[0xb003e000,0xb003ffff] dummy read-write-port= =0A= connect-bus cpu-mapper pinmux:[0xb0038000,0xb0039fff] dummy read-write-port= =0A= connect-bus cpu-mapper iop:[0xb0020000,0xb0021fff] dummy read-write-port=0A= ------=_NextPart_000_000F_01C5733C.EBB66B80 Content-Type: application/octet-stream; name="smp.conf" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="smp.conf" Content-length: 4705 # Load libraries load libcache.la cache_component_library load libcgencpu.la cgen_component_library load libmmu.la mmu_component_library load libinterrupt.la interrupt_component_library # Allocate components new hw-cpu-crisv32 cpu2 new hw-mmu-crisv32 insn-mmu2 new hw-mmu-crisv32 data-mmu2 new hw-cache-dummy icache new hw-cache-dummy dcache new hw-cache-dummy icache2 new hw-cache-dummy dcache2 new hw-interrupt-crisv32 irq2 new hw-timer-crisv32 timer2 # Global connections connect-pin hw-reset-net output-0 -> cpu2 reset! connect-pin hw-reset-net output-1 -> insn-mmu2 reset connect-pin hw-reset-net output-2 -> data-mmu2 reset connect-pin yield-net output-0 -> cpu2 yield # Scheduler connect-pin target-sched 0-event -> cpu2 step! connect-pin target-sched 0-control <- cpu2 step-cycles connect-pin target-sched time-query <- cpu2 time-query connect-pin target-sched time-high -> cpu2 time-high connect-pin target-sched time-low -> cpu2 time-low # Override settings from linux.conf disconnect-bus insn-mmu all cpu-mapper access-port disconnect-bus data-mmu all cpu-mapper access-port connect-bus insn-mmu all icache upstream connect-bus data-mmu all dcache upstream set cpu crisv32-start-address 0 # CPU set cpu2 step-insn-count 10000 set cpu2 engine-type pbb set cpu2 endian little set cpu2 crisv32-start-address 0 # MMUs connect-bus insn-mmu2 all icache2 upstream connect-bus data-mmu2 all dcache2 upstream connect-bus cpu2 insn-memory insn-mmu2 access-port connect-pin cpu2 user -> insn-mmu2 user connect-pin cpu2 pid -> insn-mmu2 pid connect-pin cpu2 enable-insn-mmu -> insn-mmu2 enable connect-bus cpu2 support-function-register-bank-1 insn-mmu2 registers connect-pin insn-mmu2 refill_fault -> cpu2 insn-refill-fault connect-pin insn-mmu2 invalid_fault -> cpu2 insn-invalidaddr-fault connect-pin insn-mmu2 access_fault -> cpu2 insn-access-fault connect-pin insn-mmu2 ex_fault -> cpu2 insn-ex-fault connect-pin insn-mmu2 fault_address -> cpu2 insn-fault-address set insn-mmu2 accesses-are-fetches true connect-bus cpu2 data-memory data-mmu2 access-port connect-pin cpu2 user -> data-mmu2 user connect-pin cpu2 pid -> data-mmu2 pid connect-pin cpu2 enable-data-mmu -> data-mmu2 enable connect-bus cpu2 support-function-register-bank-2 data-mmu2 registers connect-pin data-mmu2 refill_fault -> cpu2 data-refill-fault connect-pin data-mmu2 invalid_fault -> cpu2 data-invalidaddr-fault connect-pin data-mmu2 access_fault -> cpu2 data-access-fault connect-pin data-mmu2 we_fault -> cpu2 data-we-fault connect-pin data-mmu2 fault_address -> cpu2 data-fault-address # Cache connect-bus icache downstream cpu-mapper access-port connect-bus dcache downstream cpu-mapper access-port connect-pin dcache write_miss -> cpu dcache-write-miss connect-pin cpu dcache-abort-write -> dcache abort connect-bus icache2 downstream cpu-mapper access-port connect-bus dcache2 downstream cpu-mapper access-port connect-pin dcache2 write_miss -> cpu2 dcache-write-miss connect-pin cpu2 dcache-abort-write -> dcache2 abort connect-pin dcache write_out -> dcache2 write_in connect-pin dcache2 write_out -> dcache write_in # Timer connect-pin hw-reset-net output-0 -> timer2 reset connect-pin timer2 timer0-control -> target-sched 3-control connect-pin target-sched 3-event -> timer2 timer0-event connect-pin timer2 timer1-control -> target-sched 4-control connect-pin target-sched 4-event -> timer2 timer1-event connect-pin timer2 trig-control -> target-sched 5-control connect-pin target-sched 5-event -> timer2 trig-event connect-pin timer2 watchdog-control -> target-sched 6-control connect-pin target-sched 6-event -> timer2 watchdog-event connect-pin timer2 nmi -> cpu2 nmi set timer2 slowdown 2 set timer2 speedup 1 set timer2 nmi_polarity 1 # Interrupt connect-pin hw-reset-net output-0 -> irq2 reset connect-pin dma0 irq_out -> irq2 irq6 connect-pin dma1 irq_out -> irq2 irq7 connect-pin dma2 irq_out -> irq2 irq8 connect-pin dma3 irq_out -> irq2 irq9 connect-pin dma4 irq_out -> irq2 irq10 connect-pin dma5 irq_out -> irq2 irq11 connect-pin dma6 irq_out -> irq2 irq12 connect-pin dma7 irq_out -> irq2 irq13 connect-pin dma8 irq_out -> irq2 irq14 connect-pin dma9 irq_out -> irq2 irq15 connect-pin ser0 irq_out -> irq2 irq19 connect-pin ser1 irq_out -> irq2 irq20 connect-pin ser2 irq_out -> irq2 irq21 connect-pin ser3 irq_out -> irq2 irq22 connect-pin timer2 irq -> irq2 irq26 connect-pin irq2 ipi_out -> irq2 irq30 connect-pin irq ipi_out -> irq irq30 connect-pin irq2 irq_out -> cpu2 irq connect-bus cpu2 irq_vector irq2 irq_vector set irq2 polarity 1 # Memory map connect-bus cpu-mapper irq2:[0xb005c000,0xb005dfff] irq2 registers connect-bus cpu-mapper timer2:[0xb005e000,0xb005ffff] timer2 registers ------=_NextPart_000_000F_01C5733C.EBB66B80--