From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16608 invoked by alias); 23 Aug 2002 11:14:38 -0000 Mailing-List: contact sid-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: sid-owner@sources.redhat.com Received: (qmail 16597 invoked from network); 23 Aug 2002 11:14:36 -0000 Received: from unknown (HELO www.jennic.com) (213.143.5.74) by sources.redhat.com with SMTP; 23 Aug 2002 11:14:36 -0000 Received: from jensun01.jennic.com (jensun01.jennic.com [99.99.98.151]) by www.jennic.com (8.9.3/8.9.3) with ESMTP id LAA21722 for ; Fri, 23 Aug 2002 11:39:31 +0100 Received: from jenpc60 (jenpc60 [99.99.98.60]) by jensun01.jennic.com (8.9.3/8.9.3) with SMTP id MAA05931 for ; Fri, 23 Aug 2002 12:14:36 +0100 (BST) From: "Robert Cragie" To: Subject: FW: Trying to run on pid7t board Date: Fri, 23 Aug 2002 04:14:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2615.200 Importance: Normal X-SW-Source: 2002-q3/txt/msg00026.txt.bz2 I have done some more debugging on the problem I reported earlier regarding exception handling in the ARM pid7t implementation. It actually threw an abort_prefetch exception. I did a trace-semantics on what SID was doing and it works fine until trying to return from exception: 0x8240: LDR_PRE_INC_IMM_OFFSET gr[0]:=0x13 0x8244: MSR_S spsr:=0x13 0x8248: AND_IMM gr[1]:=0x13 0x824c: CMP_IMM zbit:=0x1 nbit:=0x0 cbit:=0x1 vbit:=0x0 0x8250: X_INVALID 0x4: AND_REG_IMM_SHIFT gr[0]:=0x13 0x8: AND_REG_IMM_SHIFT gr[0]:=0x13 0xc: LDR_PRE_INC_IMM_OFFSET pc:=0x81ac (it has now hit breakpoint at 0x81ac i.e. abort_prefetch exception handler) The instruction at 0x8250 is: ldmeqfd sp,{r0-r14,pc}^ The opcode for this is 0x08ddffff, which looks like |COND|<4>|P|U|S|W|L| Rn | Reglist | ------------------------------------------ |0000|100|0|1|1|0|1|1101|1111111111111111| ------------------------------------------ | EQ | |FD |^| |L| sp | r0-r14,pc | I confess I know very little about this, but I notice in CGEN, in arm7.cpu, only two ldmia's are supported (PUSWL = 01001 and PUSWL = 01011). The opcode above (PUSWL: 01101) (i.e. restore user mode banked registers) is not included, so does this need to be in here too in some guise? Would this be causing the invalid prefetch? Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 -----Original Message----- From: sid-owner@sources.redhat.com [mailto:sid-owner@sources.redhat.com]On Behalf Of Robert Cragie Sent: 22 August 2002 18:09 To: Frank Ch. Eigler Cc: sid@sources.redhat.com Subject: RE: Trying to run on pid7t board [snip] With some further juggling of eCos configuration, I have got it printing to the gdb console (-uart1:gdb), to the console sid was run from (-uart1:stdio) and the tksm tty window. Excellent! Now I am having problems with the timer-related calls (cyg_thread_delay() etc.) - I notice in the list this was also seen by Cristiano Pereira (04-Mar-02). I have done some debugging, and timer interrupt seems to fire once, then a data_abort exception is thrown a bit later; looks like the pc was 0xe59d0044. Ho hum. I will try to get to the bottom of what is going on - if anyone has any ideas, I'd appreciate them.