Re: Hitachi djprobe mechanism

[Mathieu Desnoyers <compudj@krystal.dyndns.org>]

Well, it seems that it has all been thought about before us, thanks to Richard
Moore.

* Keshavamurthy Anil S (anil.s.keshavamurthy@intel.com) wrote:
 
> However I have one more issues to mentioni(for discussion sake), when we have several nop 
> instructions(may be 4 nop instruction) in a landing zone, we have no guarantee that 
> all of these nop instructions are with in a page boundary. This is very important
> because when you replace these instruction with a 5 byte jump instruction, this
> 5 byte jump instruction should be with in a page boundary else the processor
> will generate unaligned instruction access voilation

Well, a "push current interrupt register value", followed by ".align 8,0x90" 
and then followed by cli, nop nop nop nop should do the trick. The far jmp is
aligned on 8 bytes memory address, right ?

> or it might
> generate page fault while trying to execute an instruction which is a very bad thing.

In the kernel, I would be very surprised to see that. In fact, even module.c,
which loads kernel code in virtual memory, only keeps it temporarily in this
location. It is put in kmalloc'd memory before the code is actually running.
Anyways, from IA-32 documentation, faults handler are called prior to execute
the instruction. It shouldn't be any different from having to call an unaligned
instruction fault handler and then a page fault handler from this first handler.
Well, all this looks ugly anyway, no wonder why they do not keep kernel code in
virtual memory.

And as the jmp instruction is 5 bytes, there seems to be no hope to find an
atomic operation that will write that.


Mathieu


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